W83176G-733 データシートの表示（PDF） - Winbond
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W83176G-733 Datasheet PDF : 14 Pages
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W83176R-733/W83176G-733
DUAL BANK DDR BUFFER FOR VIA CHIPSET
7.4 REGISTER 8 ~ Register 17 RESERVED
7.5 Skew step reference Table
SKEW<2:0>/<1:0>
000
001
010
011
100
101
110
111
DELAY TIME (PS)
0
250
500
750
1000
1250
1500
1750
7.6 Register 18: Skew Control (Default: 88h)
BIT
NAME
7 Reserved
6 DDRA_TSKEW<2>
5 DDRA_TSKEW<1>
4 DDRA_TSKEW<0>
3 Reserved
2 DDRA_CSKEW<2>
1 DDRA_CSKEW<1>
0 DDRA_CSKEW<0>
PWD
1
0
0
0
1
0
0
0
DESCRIPTION
Reserved
DDRA True clock outputs with FB_OUTA True clock
SKEW control bits
Reserved
DDRA Complementary clock outputs with FB_OUTA True
clock SKEW control bits
7.7 Register 19: Skew Control (Default: 80h)
BIT
NAME
7 Reserved
6 DDRB_CSKEW<2>
5 DDRB_CSKEW<1>
4 DDRB_CSKEW<0>
3 FAOUT_SKEW<1>
2 FAOUT_SKEW<0>
1 FBOUT_SKEW<1>
0 FBOUT_SKEW<0>
PWD
1
0
0
0
0
0
0
0
DESCRIPTION
Reserved
DDRB Complementary clock outputs with FB_OUTB True
clock SKEW control bits
FB_OUTA, DDRA clock outputs with BUF_INA clock
SKEW control bits
FB_OUTB, DDRB clock outputs with BUF_INB clock
SKEW control bits
Publication Release Date: March, 2006
-5-
Revision 1.0
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