VT82C596 データシートの表示（PDF） - Unspecified
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VT82C596 Datasheet PDF : 96 Pages
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Table 7. AC Characteristics - UltraDMA-33 IDE Bus Interface Timing
VT82C596B
Symbol
TENV1
TDS1
TDH1
TENV2
TDVS2
TDVH2
TDVS2
TDVH2
TRFS
TRP
TLI4
TLI4
TZA4
TDVS4
TDVH4
TLI5
TLI5
TMIL5
TDVS5
TDVH5
TMIL6
TZA6
TLI5
TMIL5
T2
T3
T4
T5
TWDS
TWDH
TRDS
TRDH
Description
Envelope time for read initial
Data setup time for read initial
Data hold time for read initial (rise)
Envelope time for write initial (rise)
Data setup time for write initial (fall)
Data hold time for write initial (fall)
Data setup time for write initial
Data hold time for write initial
READY to final STROBE time
READY to Pause time
Limited interlock time (to STOP)
Limited interlock time (to Host DMARDY)
Delay time required for output drives turning on
Data setup time for read terminating
Data hold time for read terminating
Limited interlock time (to STOP)
Limited interlock time (to Host STROBE)
Limited interlock time with minimum
Data setup time for write terminating
Data hold time for write terminating
Limited interlock time with minimum
Delay time required for output drives turning on
Limited interlock time
Limited interlock time with minimum
Delay time of PCLK to DCS3,1#
Delay time of PCLK to DA[2:0]
Delay time of PCLK to DIOW#
Delay time of PCLK to DIOR#
Data setup time during PIO write
Data hold time during PIO write
Data setup time during PIO read
Data hold time during PIO read
Timing
Unit
29.3
ns
1.1
ns
2.3
ns
29.3
ns
42.2
ns
17.8
ns
42.0
ns
17.2
ns
21.3
ns
180.0
ns
95.1
ns
125.3
ns
102.0
ns
55.3
ns
31.6
ns
125.3
ns
95.2
ns
120.6
ns
57.7
ns
31.8
ns
155.8
ns
68.5
ns
65.2
ns
90.6
ns
4.8
ns
5.3
ns
9.3
ns
9.2
ns
85.5
ns
31.7
ns
0.4
ns
2.1
ns
Revision 0.3 June 17, 1999
-84-
Electrical Specifications
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