VT82C596 データシートの表示（PDF） - Unspecified

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VT82C596

PCI INTEGRATED PERIPHERAL CONTROLLER

Unspecified 

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I/O Offset 3B-38 - GP Timer Reload Enable ..................RW

All bits in this register default to 0 on power up.

31-11 Reserved ..........................................always read 0

7 Enable GP1 Timer Reload on KBC Access

1 = setting of KBC_STS causes GP1 timer to reload.

6 Enable GP1 Timer Reload on Serial Port Access

1 = setting of COMA_STS or COMB_STScauses

GP1 timer to reload.

5 Reserved ..........................................always read 0

4 Enable GP1 Timer Reload on VGA Access

1 = setting of VGA_STS causes GP1 timer to reload.

3 Enable GP1 Timer Reload on IDE/Floppy Access

1 = setting of FLP_STS, PIDE_STS, or SIDE_STS

causes GP1 timer to reload.

2 Ena GP3 Timer Reload on GPIO Range 1 Access

1 = setting of GR1_STS causes GP3 timer to reload.

1 Ena GP2 Timer Reload on GPIO Range 0 Access

1 = setting of GR0_STS causes GP2 timer to reload.

0 Enable GP0 Timer Reload on Primary Activity

1 = setting of PACT_STS causes GP0 timer to reload.

Primary activities are enabled via the Primary

Activity Detect Enable register (offset 37-34) with

status recorded in the Primary Activity Detect Status

register (offset 33-30).

VT82C596B

General Purpose I/O Registers

I/O Offset 45-44 – External SMI Input Value

(EXTSMI_VAL) ................................................................ RO

Depending on the configuration, up to 8 external SCI/SMI

ports are available as indicated below. The state of these

inputs may be read in this register.

15-11 Reserved ........................................always reads 0

10 Hardware Monitor IRQ Status

9 SMBus IRQ Status

8 SMBus Resume Status

7 RI# (GPI12 Pin) Input Value

6 SMBALRT# (GPI11 Pin) Input Value

5 Reserved ........................................always reads 0

4 SLPBTN# (GPI13 Pin) Input Value

3 LID (GPI10 Pin) Input Value

2 BATLOW# (GPI9 Pin) Input Value

1 PME# (GPI1 Pin) Input Value

0 EXTSMI# Input Value

I/O Offset 4B-48 - GPI Port Input Value (GPI_VAL).... RO

31-22 Reserved ......................................... always read 0

21-0 GPI[21-0] Input Value ............................. Read Only

I/O Offset 4F-4C - GPO Port Output Value (GPO_VAL)RW

Reads from this register return the last value written (held on

chip)

31 Reserved ........................................always reads 0

30-0 GPO[30-0] Output Value..........default = 7FFFFFFh

Revision 0.3 June 17, 1999

-77-

Function 3 Registers - Power Management and SMBus

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