VT82C596 データシートの表示（PDF） - Unspecified

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VT82C596

PCI INTEGRATED PERIPHERAL CONTROLLER

Unspecified 

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VT82C596B

I/O Offset 33-30 - Primary Activity Detect Status.......RWC

These bits correspond to the Primary Activity Detect Enable

bits in offset 37-34.

31-11 Reserved ..........................................always read 0

10 Audio Controller Access Status ........... (AUD_STS)

Set if the audio controller is accessed.

9 Keyboard Controller Access Status..... (KBC_STS)

Set if the keyboard controller is accessed via I/O port

60h.

8 VGA Access Status................................ (VGA_STS)

Set if the VGA port is accessed via I/O ports 3B0-

3DFh or memory space A0000-BFFFFh.

7 Parallel Port Access Status....................(PAR_STS)

Set if the parallel port is accessed via I/.O ports 278-

27Fh or 378-37Fh (LPT2 or LPT1).

6 Serial Port B Access Status .............. (COMB_STS)

Set if serial port B is accessed via I/O ports 2F8-2FFh

or 2E8-2EFh.

5 Serial Port A Access Status .............. (COMA_STS)

Set if serial port A is accessed via I/O ports 3F8-3FFh

or 3E8-3EFh.

4 Floppy Access Status.............................. (FLP_STS)

Set if the floppy devices are accessed via I/O ports

3F0-3F5h or 3F7h.

3 Secondary IDE Access Status...............(SIDE_STS)

Set if the secondary IDE port is accessed via I/O

ports 170-177h or 376h.

2 Primary IDE Access Status ................. (PIDE_STS)

Set if the primary IDE port is accessed via I/O ports

1F0-1F7h or 3F6h.

1 Primary Interrupt Activity Status...... (PIRQ_STS)

Set on the occurrence of a primary interrupt (enabled

via the "Primary Interrupt Channel" register at

Function 3 PCI configuration register offset 44h).

0 PCI Master Activity Status .................... (PCI_STS)

Set on the occurrence of PCI master activity.

Note: The bits above correspond to the bits of the Primary

Activity Detect Enable register at offset 34 (see right

hand column of this page): if the corresponding bit is

set in that register, setting of the above bits will cause

the PACT_STS bit to be set (bit-0 of the Global

Status register at offset 28). Setting of PACT_STS

may be set up to enable a "Primary Activity Event":

an SMI will be generated if PACT_EN is set (bit-0 of

the Global Enable register at offset 2Ah) and/or the

GP0 timer will be reloaded if the "GP0 Timer Reload

on Primary Activity" bit is set (bit-0 of the GP Timer

Reload Enable register at offset 38 on this page).

Note: Bits above also correspond to bits of the GP Timer

Reload Enable register at offset 38: if the

corresponding bit is set in that register, setting the bit

in this register will cause the indicated timer to be

reloaded.

Bits in this register are set by hardware only and may only be

cleared by writing a 1 to the desired bit. All bits default to 0.

I/O Offset 37-34 - Primary Activity Detect Enable ........ RW

These bits correspond to the Primary Activity Detect Status

bits in offset 33-30.

31-11 Reserved ......................................... always read 0

10 Audio Controller Status Enable ............ (AUD_EN)

0 Don't set PACT_STS if AUD_STS is set .... def

1 Set PACT_STS if AUD_STS is set

9 Keyboard Controller Status Enable ..... (KBC_EN)

0 Don't set PACT_STS if KBC_STS is set..... def

1 Set PACT_STS if KBC_STS is set

8 VGA Status Enable ................................ (VGA_EN)

0 Don't set PACT_STS if VGA_STS is set .... def

1 Set PACT_STS if VGA_STS is set

7 Parallel Port Status Enable ....................(PAR_EN)

0 Don't set PACT_STS if PAR_STS is set ..... def

1 Set PACT_STS if PAR_STS is set

6 Serial Port B Status Enable ................(COMB_EN)

0 Don't set PACT_STS if COMB_STS is set . def

1 Set PACT_STS if COMB_STS is set

5 Serial Port A Status Enable ............... (COMA_EN)

0 Don't set PACT_STS if COMA_STS is set . def

1 Set PACT_STS if COMA_STS is set

4 Floppy Status Enable .............................. (FLP_EN)

0 Don't set PACT_STS if FLP_STS is set ...... def

1 Set PACT_STS if FLP_STS is set

3 Secondary IDE Status Enable ...............(SIDE_EN)

0 Don't set PACT_STS if SIDE_STS is set .... def

1 Set PACT_STS if SIDE_STS is set

2 Primary IDE Status Enable ...................(PIDE_EN)

0 Don't set PACT_STS if PIDE_STS is set.... def

1 Set PACT_STS if PIDE_STS is set

1 Primary INTR Status Enable ............... (PIRQ_EN)

0 Don't set PACT_STS if PIRQ_STS is set.... def

1 Set PACT_STS if PIRQ_STS is set

0 PCI Master Status Enable ..................... (DRQ_EN)

0 Don't set PACT_STS if PCI_STS is set....... def

1 Set PACT_STS if PCI_STS is set

Note: Setting of any of the above bits also sets the

PACT_STS bit (bit-0 of offset 28) which causes the

GP0 timer to be reloaded (if PACT_GP0_EN is set)

or generates an SMI (if PACT_EN is set).

Revision 0.3 June 17, 1999

-76-

Function 3 Registers - Power Management and SMBus

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