VT82C596 データシートの表示（PDF） - Unspecified
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コンポーネント説明
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VT82C596 Datasheet PDF : 96 Pages
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Interrupt Controller Registers
Ports 20-21 - Master Interrupt Controller
The Master Interrupt Controller controls system interrupt
channels 0-7. Two registers control the Master Interrupt
Controller. They are:
I/O Address Bits 15-0 Register Name
0000 0000 001x xxx0 Master Interrupt Control
RW
0000 0000 001x xxx1 Master Interrupt Mask
RW
Note that not all bits of the address are decoded.
The Master Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports A0-A1 - Slave Interrupt Controller
The Slave Interrupt Controller controls system interrupt
channels 8-15. The slave system interrupt controller also
occupies two register locations:
I/O Address Bits 15-0 Register Name
0000 0000 101x xxx0 Slave Interrupt Control
RW
0000 0000 101x xxx1 Slave Interrupt Mask
RW
Note that not all address bits are decoded.
The Slave Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
VT82C596B
Interrupt Controller Shadow Registers
The following shadow registers are enabled by setting bit 4 of
Rx47 to 1 (offset 47h in the PCI-ISA Bridge function 0
register group). If the shadow registers are enabled, they are
read back at the indicated I/O port instead of the standard
interrupt controller registers (writes to the interrupt controller
register ports are directed to the standard interrupt controller
registers).
Port 20 - Master Interrupt Control Shadow ................... RO
7-5 Reserved ........................................always reads 0
4 OCW3 bit 5
3 OCW2 bit 7
2 ICW4 bit 4
1 ICW4 bit 1
0 ICW1 bit 3
Port 21 - Master Interrupt Mask Shadow ....................... RO
7-5 Reserved ........................................always reads 0
4-0 T7-T3 of Interrupt Vector Address
Port A0 - Slave Interrupt Control Shadow ..................... RO
7-5 Reserved ........................................always reads 0
4 OCW3 bit 5
3 OCW2 bit 7
2 ICW4 bit 4
1 ICW4 bit 1
0 ICW1 bit 3
Port A1 - Slave Interrupt Mask Shadow ........................ RO
7-5 Reserved ........................................always reads 0
4-0 T7-T3 of Interrupt Vector Address
Timer / Counter Registers
Ports 40-43 - Timer / Counter Registers
There are 4 Timer / Counter registers:
I/O Address Bits 15-0 Register Name
0000 0000 010x xx00 Timer / Counter 0 Count
RW
0000 0000 010x xx01 Timer / Counter 1 Count
RW
0000 0000 010x xx10 Timer / Counter 2 Count
RW
0000 0000 010x xx11 Timer / Counter Cmd Mode WO
Note that not all bits of the address are decoded.
The Timer / Counters are compatible with the Intel 8254
Timer / Counter chip. Detailed descriptions of 8254 Timer /
Counter operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Revision 0.3 June 17, 1999
-33-
Register Descriptions - Legacy I/O Ports
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