VT82C586B データシートの表示（PDF） - Unspecified

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VT82C586B

PCI Integrated Peripheral Controller

Unspecified 

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VT82C586B

Signal Name

PCLK

FRAME#

AD[31:0]

C/BE[3:0]#

IRDY#

TRDY#

STOP#

DEVSEL#

PAR

SERR#

IDSEL

PIRQA-D#

PREQ#

PGNT#

Pin No.

2

181

204-199, 196-

195, 192-189,

187-185, 183,

172, 170-167,

165-163, 161-

158, 155-152

194, 182, 173,

162

180

179

176

178

174

175

193

1, 207-205

151

150

PCI Bus Interface

I/O Signal Description

I PCI Clock. PCLK provides timing for all transactions on the PCI Bus.

B Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates

that one more data transfer is desired by the cycle initiator.

B Address/Data Bus. The standard PCI address and data lines. The address is driven

with FRAME# assertion and data is driven or received in following cycles.

B Command/Byte Enable. The command is driven with FRAME# assertion. Byte

enables corresponding to supplied or requested data are driven on following clocks.

B Initiator Ready. Asserted when the initiator is ready for data transfer.

B Target Ready. Asserted when the target is ready for data transfer.

B Stop. Asserted by the target to request the master to stop the current transaction.

B Device Select. The VT82C586B asserts this signal to claim PCI transactions through

positive or subtractive decoding.

B Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

I System Error. SERR# can be pulsed active by any PCI device that detects a system

error condition. Upon sampling SERR# active, the VT82C586B can be programmed

to generate an NMI to the CPU.

I Initialization Device Select. IDSEL is used as a chip select during configuration

read and write cycles.

I PCI Interrupt Request. These pins are typically connected to the PCI bus INTA#-

INTD# pins as follows:

PIRQA# PIRQB# PIRQC# PIRQD#

PCI Slot 1 INTA# INTB# INTC# INTD#

PCI Slot 2 INTB# INTC# INTD# INTA#

PCI Slot 3 INTC# INTD# INTA# INTB#

PCI Slot 4 INTD# INTA# INTB# INTC#

O PCI Request. This signal goes to the North Bridge to request the PCI bus.

I PCI Grant. This signal is driven by the North Bridge to grant PCI access to the

VT82C586B.

Revision 1.0 May 13, 1997

-6-

Pinouts

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