V62C51864 データシートの表示（PDF） - Mosel Vitelic Corporation

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V62C51864

8K X 8 STATIC RAM

Mosel Vitelic Corporation  

MOSEL VITELIC

Switching Waveforms (Write Cycle)

Write Cycle 1 (WE Controlled)(4)

ADDRESS

CE1

CE2

WE

OUTPUT

INPUT

tAS

tWHZ

tWC

tCW(6)

tAW

tCW(6)

tWP(1)

tDW

Write Cycle 2 (CE Controlled)(4)

ADDRESS

CE1

CE2

WE

tWC

(4)

tAW

tAS

tCW(6)

tCW(6)

V62C51864

tWR(2)

tDH

51864 12

tWR(2)

OUTPUT

High-Z

INPUT

tDW

tDH

(5)

51864 13

NOTES:

1. The internal write time of the memory is defined by the overlap of1CaEnd CE2 active and WElow. Both signals must be active to

initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to

the second transition edge of the signal that terminates the write.

2. tWR is measured from the earlier of CE1 or WE going HIGH, or CE2 going LOW at the end of the write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

4. OE = VIL or VIH. However it is recommended to keep OEat VIH during write cycle to avoid bus contention.

5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase

to the outputs must not be applied to them.

6. tCW is measured from CE1 going LOW or CE2 going HIGH to the end of write.

V62C51864 Rev. 2.1 June 1998

8

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