V29C51400T-12T データシートの表示（PDF） - Mosel Vitelic Corporation
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V29C51400T-12T
Mosel Vitelic Corporation
V29C51400T-12T Datasheet PDF : 16 Pages
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MOSEL VITELIC
V29C51400T/V29C51400B
Sector Erase Cycle
The V29C51400T/V29C51400B features a sector
erase operation which allows each sector to be
erased and reprogrammed without affecting data
stored in other sectors. Sector erase operation is
initiated by using a specific six-bus-cycle sequence:
Two unlock program cycles, a setup command, two
additional unlock program cycles, and the sector
erase command (see Table 2). A sector must be first
erased before it can be re-written. While in the
internal erase mode, the device ignores any
program attempt into the device. The internal erase
completion can be determined via DATA polling or
toggle bit status.
The V29C51400T/V29C51400B is shipped fully
erased (all bits = 1).
Table 1. Operation Modes Decoding
Decoding Mode
CE
OE
WE
A0
A1
A9
I/O
Read
VIL
VIL
VIH
A0
A1
A9
READ
Byte Write
VIL
VIH
VIL
A0
A1
A9
PD
Standby
VIH
X
X
X
X
X
HIGH-Z
Autoselect Device ID
VIL
VIL
VIH
VIH
VIL
VH
CODE
Autoselect Manufacture ID
VIL
VIL
VIH
VIL
VIL
VH
CODE
Enabling Boot Block Protection Lock
VIL
VH
VIL
X
X
VH
X
Disabling Boot Block Protection Lock
VH
VH
VIL
X
X
VH
X
Output Disable
VIL
VIH
VIH
X
X
X
HIGH-Z
NOTES:
1. X = Don’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max.
2. PD: The data at the byte address to be programmed.
Table 2. Command Codes
Command
Sequence
Reset/Read
Reset/Read
Autoselect
Mode
Program
Chip Erase
Sector Erase
Word
Byte
Word
Bus
Write
Cycles
Req’d
1
3
3
Byte
Word/Byte
Word
4
Byte
Word
0
Byte
Word
6
Byte
First Bus
Program Cycle
Address Data
XXXXH F0H
5555H AAH
AAAAH
5555H AAH
AAAAH
5555H
AAAAH
5555H
AAAAH
5555H
AAAAH
AAH
AAH
AAH
Second Bus
Program Cycle
Address Data
2AAAH 55H
5555H
2AAAH 55H
5555H
2AAAH 55H
5555H
2AAAH 55H
5555H
2AAAH 55H
5555H
Third Bus
Program Cycle
Address Data
5555H F0H
AAAAH
5555H 90H
AAAAH
5555H A0H
AAAAH
5555H 80H
AAAAH
5555H 80H
AAAAH
Fourth Bus
Program Cycle
Address Data
Fifth Bus
Program Cycle
Address Data
RA
RD
01H
00H
PA
13H, B3H
(B Device
ID)
13H, B3H
(B Device
ID)
40H
(Manuf. ID)
PD(4)
5555H
AAAAH
5555H
AAAAH
AAH
AAH
2AAAH 55H
5555H
2AAAH 55H
5555H
Six Bus
Program Cycle
Address Data
5555H 10H
AAAAH
SA
30H
NOTES:
1. RA: Read Address
2. RD: Read Data
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
5. SA(5): Sector Address
Chip Erase Cycle
The V29C51400T/V29C51400B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
V29C51400T/V29C51400B Rev. 1.5 October 2000
11
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