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ST662ACD データシートの表示(PDF) - STMicroelectronics

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ST662ACD Datasheet PDF : 12 Pages
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ST662A
APPLICATION CIRCUIT
Based on fast charge/discharge of capacitors,
this circuit involves high di/dt values limited only
by Ron of switches. This implies a critical layout
design due to the need to minimize inductive
paths and place capacitors as close as possible
to the device.
A good layout design is strongly recommended
for noise reason. For best performance, use very
short connections to the capacitors and the
values shown in table 1.
C3 and C4 must have low ESR in order to
minimize the output ripple. Their values can be
reduced to 2µF and 1µF, respectively, when
using ceramic capacitors, but must be of 10µF or
larger if aluminium electrolytic are chosen.
C5 must be placed as close to the device as
possible and could be omitted if very low output
noise performance are not required.
Fig 4 and Fig 5 show, respectively, our
EVALUATION kit layout and the relatively
electrical shematic.
Figure 4: KIT Lay-out
Figure 5: Electrical Schematic
Table 1: List of Components
CAPACITOR
Charge Pump C1
Charge Pump C2
Input C3
O utput C4
Decoupling C5
6/12
TYPE
Ce r am ic
Ce r am ic
Electrolyt ic Tantalum
Electrolyt ic Tantalum
Ce r am ic
VALUE (µF)
0.22
0.22
4.7
4.7
0.1

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