UPD72870 データシートの表示（PDF） - NEC => Renesas Technology

部品番号

コンポーネント説明

メーカー

UPD72870

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72870,72871

3.1.1 Offset_00 Vendor ID Register

This register identifies the manufacturer of the µPD72870, 72871. The ID is assigned by the PCI_SIG committee.

Bits

15-0

R/W

R

Constant value of 1033H.

Description

3.1.2 Offset_02 DeviceID Register

This register identifies the type of the device for the µPD72870, 72871. The ID is assigned by NEC Corporation.

Bits

5 15-0

R/W

Description

R

Constant value of 00CDH (µPD72870 ).

Constant value of 00CEH (µPD72871).

3.1.3 Offset_04 Command Register

The register provides control over the device’s ability to generate and respond to PCI cycles.

Bits

0

1

2

3

4

5

6

7

8

9

15-10

R/W

Description

R

I/O enable Constant value of 0. The µPD72870, 72871 does not respond to PCI I/O

accesses.

R/W

Memory enable Default value of 1. It defines if the µPD72870, 72871 responds to PCI

memory accesses. This bit should be set to one upon power-up reset.

0: The µPD72870, 72871 does not respond to PCI memory cycles

1: The µPD72870, 72871 responds to PCI memory cycles

R/W

Master enable Default value of 1. It enables the µPD72870, 72871 as bus-master on the

PCI-bus.

0: The µPD72870, 72871 cannot generate PCI accesses by being a bus-master

1: The µPD72870, 72871 is capable of acting as a bus-master

R

Special cycle monitor enable Constant value of 0. The special cycle monitor is always

disabled.

R/W

Memory write and invalidate enable Default value of 0. It enables Memory Write and Invalid

Command generation.

0: Memory write must be used

1: The µPD72870, 72871, when acts as PCI master, can generate the command

R

VGA color palette invalidate enable Constant value of 0. VGA color palette invalidate is

always disabled.

R/W

Parity error response Default value of 0. It defines if the µPD72870, 72871 responds to PERR.

0: Ignore parity error

1: Respond to parity error

R

Stepping enable Constant value of 0. Stepping is always disabled.

R/W

System error enable Default value of 0. It defines if the µPD72870, 72871 responds to SERR.

0: Disable system error checking

1: Enable system error checking

R

Fast back-to-back enable Constant value of 0. Fast back-to-back transactions are only

allowed to the same agent.

R

Reserved Constant value of 000000.

24

Preliminary Data Sheet S13925EJ2V0DS00

Share Link: