UPD72870AF1 データシートの表示（PDF） - NEC => Renesas Technology

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UPD72870AF1

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72870A

3.1.23 Offset_64 Power Management Control/Status Register

This is a 16-bit read-only register that provides control status information of the µPD72870A.

Bits

1,0

R/W

Description

R/W

PowerState Default value is undefined. This field is used both to determine the current power

state of the µPD72870A and to set the µPD72870A into a new power state. As D1 is not

supported in the current implementation of the µPD72870A, writing of ‘01’ will be ignored.

00: D0 (DMA contexts: ON, Link Layer: ON)

01: Reserved (D1 state not supported)

10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon

LinkON being active)

11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon

LinkON being active, Power can be removed)

7-2

8

12-9

14,13

15

The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal

signal in the µPD72870A.

R

Reserved Constant value of 000000.

R/W

PME_En Default value of 0. This field is used to enable the specific power management

features of the µPD72870A.

R

Data_Select Constant value of 0000.

R

Data_Scale Constant value of 00.

R/W

PME_Status Default value is undefined. A write of ‘1’ clears this bit, while a write of ‘0’ is

ignored.

Preliminary Data Sheet S14653EJ1V0DS00

29

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