UPD72870AF1 データシートの表示（PDF） - NEC => Renesas Technology
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UPD72870AF1 Datasheet PDF : 52 Pages
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µPD72870A
Name
PORTDIS
I/O
Pin No.
LQFP
FBGA
I 105
H16
SUS_RESM I 106
G15
CPS
I 123
A15
Note Please refer to 4.1.3 CPS.
1.3 PHY Signals: (9 pins)
IOL
Volts(V)
Function
(2/2)
Port Disable
SUS_RESM = 1
This selected state will be loaded to Disabled bit
which allocated PHY register Port Status Page.
1:Disable
At this time, all ports will be disabled.
*3
PHY Digital
SUS_RESM = 0
PORTDIS has no effect.
Suspend/Resume Function Select
PHY Digital
1 : Suspend/Resume On (P1394a draft 2.0
compliant)
0 : Suspend/Resume Off (P1394a draft 1.3
compliant)
-
- Cable Power Status Input Note
PHY Digital
Name
I/O
Pin No.
IOL
Volts(V)
Function
LQFP
FBGA
TpBias0
O 128
C14
TpBias1
O 127
B14
TpBias2
O 126
A14
RI0
- 121
A16
RI1
- 122
B16
-
- Port-1 Twisted Pair Bias Voltage Output Note 1
-
- Port-2 Twisted Pair Bias Voltage Output Note 1
-
- Port-3 Twisted Pair Bias Voltage Output Note 1
-
- Resistor0 for Reference Current Setting Note 2
-
- Resistor1 for Reference Current Setting Note 2
FIL1
- 114
E15
-
- APLL Filter Terminal (No need to assemble)
FIL0
- 115
E16
-
- APLL Filter GND (No need to assemble)
XI
I 117
D15
-
- X’tal XI
XO
O 118
D16
-
- X’tal XO
Notes 1. If unused port, please refer to 4.1.4 Unused Ports.
2. Please refer to 4.6 RI0, RI1.
PHY Analog
PHY Analog
PHY Analog
PHY Analog
PHY Analog
PHY Analog
PHY Analog
PHY Analog
PHY Analog
1.4 PHY Control Signals: (5 pins)
Name
I/O
Pin No.
IOL
LQFP
FBGA
PC0-PC2
I 93-95
K15,L15,
-
L16
CMC
I 96
K16
-
P_RESETB I 110
F16
Notes 1. Please refer to 4.4 PC0-PC2, CMC.
2. Please refer to 4.5 P_RESETB.
Volts(V)
Function
3.3 Power Class Input Note 1
3.3 Configuration Manager Capable Note 1
PHY Power on Reset Input Note 2
PHY Digital
PHY Digital
PHY Digital
14
Preliminary Data Sheet S14653EJ1V0DS00
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