UPD72852A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72852A

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

NEC => Renesas Technology 

µPD72852A

4.4 Acceleration Control

Enable of ack-acceleration and fly-by on the same isochronous period may create a problem. The isochronous

cycle may extend unintentionally when transmitting the asynchronous packet by a node using ack-acceleration and fly-

by.

To avoid this problem, Link should control Disable/Enable of these enhancements (ack-Acceleration, fly-by), by

Acceleration Control requests. Cycle master cannot issue the Acceleration Control request.

The enhancements should not be used from the generation of the local cycle synchronization event to the

confirmation of cycle start. In this period, all Links except for Cycle Master use Acceleration Control as follows:

• Do not issue Fair nor Priority request to Link after generating local cycle synchronization, if the Acceleration

Control request’s Accelerate bit is not set to 0.

• Link must not use Hold when transmitting continuous primary asynchronous packet after the Acknowledge packet,

except after ack_pending to complete the split transaction.

• Ending the Link during the isochronous period issues the acceleration control request to set the Accelerate bit to 1,

enabling these enhancements.

The µPD72852A does not require setting the Acceleration Control during isochronous transmit to enable the

isochronous request fly-by acceleration.

It is not necessary to issue Acceleration Control request when the cycle master is absent from the serial bus. These

enhancements are enabled if the Enab_accel bit in the PHY register is set. The µPD72852A supports Variable

Acceleration controlled by the Acceleration Control during power-on reset.

Data Sheet S16725EJ2V0DS

29

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