UPD72852A データシートの表示（PDF） - NEC => Renesas Technology
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UPD72852A Datasheet PDF : 48 Pages
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µPD72852A
• Acceleration Controller
Table 4-8. Acceleration Controller Request Format
Bit
0
1-3
4
5
Type
start
request
access address
stop
Content
Signal that starts a request : 1
110 : Acc Ctrl accelerate controller
0: Accelerate disable
1: Accelerate enable
End request signal : 0
Bit
000
001
010
011
100
101
110
111
Type
ImmReq
IsoReq
PriReq
FairReq
RdReg
WrReg
AccCtrl
-
Table 4-9. Request Type List
Content
Used to acknowledge packet transmit.
When Idle is detected, PHY immediately controls the bus.
Used to transmit isochronous packet.
PHY does arbitration after isochronous gap is detected and acquires the bus.
Used for Cycle master request.
Fair request.
PHY register read request.
PHY register write request.
Disable/enable of arbitration acceleration.
Unused.
For the Link to execute Priority request and Fair, start the request using LREQ when CTL0, CTL1 becomes idle,
after one clock. When request is acknowledged, the µPD72852A outputs Grant to CTL0, CTL1.
The Link of cycle master uses PriReq to transmit the cycle start packet. IsoReq transmits the isochronous
packet.
IsoReq becomes effective only as follows:
• The transmission of the cycle start packet is performed on the same isochronous period as Receive. (The
period until the subaction gap is detected.)
• During isochronous packet Transmit or Receive.
The µPD72852A cancels IsoReq with the subaction gap detection or bus reset. To meet the timing, do not
issue the IsoReq to PHY when CRC operation is performed.
The Link cancel method is described later.
After the packet is received, Link issues ImmReq as the acknowledge packet transmission. The purpose is to
prevent another node from detecting subaction gap as ACK_RESPONSE_TIME. The µPD72852A acquires the
bus after packet receive and returns Grant to CTL0, CTL1. When CRC fails, before Link detects Grant, assert 3
Idle cycles to CTL0, CTL1.
When the bus reset is generated, the unprocessed requests are canceled.
The µPD72852A updates the data of the Write request register and the contents of the Read register are
changed. The contents of the register of the specified address are output to the Link as a status transfer in the
Read request register, When the status transmission is interrupted by transmitting/receiving packets, the status
transmission will re-start from the first bit after completing the transmit/receive of the packets.
The bus request (ImmReq, IsoReq, PriReg, FairReq) is completed (in case of ImmReq, IsoReq, when the
subaction gap is detected) when the packet is transmitted or canceled by canceling the bus request.
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Data Sheet S16725EJ2V0DS
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