UPD72873 データシートの表示（PDF） - NEC => Renesas Technology

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UPD72873

IEEE1394 OHCI 1.1 COMPLIANT 2PORT PHY-LINK 1-CHIP HOST CONTROLLER

NEC => Renesas Technology 

µPD72873

1.8 VDD

Name

I/O

Pin No.

IOL

Volts(V)

Function

Block *

PCI_VDD

- 19, 60

-

5/3.3 VDD for PCI I/Os

Link

L_VDD

- 1, 14, 25, 31, 43,

-

3.3 VDD for Link digital Core and Link I/Os

Link

51, 64

To use D3cold wake up function, L_VDD must switch

VDD to Vaux when the system suspend.

P_DVDD

- 73, 79, 82

-

3.3 PHY digital VDD

PHY Digital

P_AVDD

- 86, 90, 95,

110 to 112

-

3.3 PHY Analog VDD

PHY Analog

Remark *: If the Link pin is pulled up, it should be connected to L_VDD.

If the PHY Digital pin is pulled up, it should be connected to P_DVDD.

If the PHY Analog pin is pulled up, it should be connected to P_AVDD.

1.9 GND

Name

GND

I/O

Pin No.

- 11, 20, 30, 38, 46,

54, 61, 69, 83, 84,

89, 94, 106 to 109,

113, 120

IOL

Volts(V)

-

- GND

Function

Block

-

12

Preliminary Data Sheet S15305EJ2V0DS

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