UPD161643 データシートの表示（PDF） - NEC => Renesas Technology

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UPD161643

176-OUTPUT TFT-LCD GATE DRIVER

NEC => Renesas Technology 

µPD161643

Electrical Characteristics (TA = −40 to +85°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = −15 V, VSS = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Output ON Resistance

Input Current

Dynamic Current 1

Dynamic Current 2

Dynamic Current 3

Static Current Note

VIH1

VIL1

VOH

VOL

RON1

RON2

II1

ICC1

IT

IEE

ISS

R,/L, CLK, STVR, STVL, OE1, OE2,

0.8 VCC1

STVSEL, OE1SEL, OE2SEL

0

STVR, STVL, IOH = –40 µA

VCC1 – 0.4

STVR, STVL, IOH = +40 µA

0

O1 to O176, VOUT = VT − 0.5 V

5.0

O1 to O176, VOUT = VEE + 0.5 V

5.0

Logic input pin

VCC1, Note

VT, Note

VEE, Note

VCC1, VT in stand-by mode

VCC1

V

0.2 VCC1

V

VCC1

V

0.4

V

7.5

kΩ

7.5

kΩ

±1.0

µA

200

µA

100

µA

100

µA

10

µA

Note fCLK = 20 kHz, frame frequency = 60 Hz, output no load

Switching Characteristics (TA = −40 to +85°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = −15 V, VSS = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Cascade Output Delay Time

5 Driver Output Delay Time 1

5 Driver Output Delay Time2

5 Driver Output Delay Time 3

5 Output Rise Time

tPHL1

tPLH1

tPHL2

tPLH2

tPHL3

tPLH3

tPHL4

tPLH4

tTLH

CL = 20 pF,

CLK → STVL (STVR)

CL = 50 pF,

CLK → On

CL = 50 pF,

OE1 → On

CL = 50 pF,

OE2 → On

CL = 50 pF

800

ns

800

ns

1.5

µs

1.5

µs

1.5

µs

1.5

µs

1.5

µs

1.5

µs

1.5

µs

Output Fall Time

tTHL

1.5

µs

Input Capacitance

CI

TA = 25°C

15

pF

Clock Frequency

fCLK

When connected in cascade

20

100

kHz

Timing Requirement (TA = −40 to +85°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = −15 V, VSS = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Clock Pulse High Period

PWCLK(H)

500

ns

Clock Pulse Low Period

PWCLK(L)

500

ns

Enable Pulse High Period

PWOE

OE1, OE2

1

µs

Data Setup Time

tSETUP

STVR (STVL) ↓ → CLK ↑

200

ns

Data Hold Time

tHOLD

CLK ↑ → STVR (STVL) ↑

200

ns

Remark The rise and fall times of logic input must be tr = tf = 20 ns (10 to 90%)

Data Sheet S15796EJ1V0DS

13

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