UJA1079 データシートの表示（PDF） - NXP Semiconductors.

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UJA1079

LIN core system basis chip

NXP Semiconductors. 

NXP Semiconductors

UJA1079

LIN core system basis chip

6.1.2 Off mode

The SBC switches to Off mode from all other modes if the battery supply drops below the

power-off detection threshold (Vth(det)poff). In Off mode, the voltage regulator is disabled

and the bus system is in a high-resistive state.

As soon as the battery supply rises above the power-on detection threshold (Vth(det)pon),

the SBC goes to Standby mode, and a system reset is executed (reset pulse width of

tw(rst), long or short; see Section 6.5.1 and Table 11).

6.1.3 Standby mode

The SBC will enter Standby mode:

• From Off mode if VBAT rises above the power-on detection threshold (Vth(det)pon)

• From Sleep mode on the occurrence of a LIN or local wake-up event

• From Overtemp mode if the chip temperature drops below the overtemperature

protection release threshold, Tth(rel)otp

• From Normal mode if bit MC is set to 00 or a system reset is performed (see

Section 6.5)

In Standby mode, V1 is switched on. The LIN transceiver will either be in a low-power

state (Lowpower mode; STBCL = 1; see Table 6) with bus wake-up detection enabled or

completely switched off (Off mode; STBCL = 0) - see Section 6.7.1. The watchdog can be

running in Timeout mode or Off mode, depending on the state of the WDOFF pin and the

setting of the watchdog mode control bit (WMC) in the WD_and_Status register (Table 4).

The SBC will exit Standby mode if:

• Normal mode is selected by setting bits MC to 10 or 11

• Sleep mode is selected by setting bits MC to 01

• The chip temperature rises above the OTP activation threshold, Tth(act)otp, causing the

SBC to enter Overtemp mode

6.1.4 Normal mode

Normal mode is selected from Standby mode by setting bits MC in the Mode_Control

register (Table 5) to 10 or 11.

In Normal mode, the LIN physical layer (LIN) will be enabled (Active mode; STBCL = 0;

see Table 6) or in a low-power state (Lowpower mode; STBCL = 1) with bus wake-up

detection active.

The SBC will exit Normal mode if:

• Standby mode is selected by setting bits MC to 00

• Sleep mode is selected by setting bits MC to 01

• A system reset is generated (see Section 6.1.3; the SBC will enter Standby mode)

• The chip temperature rises above the OTP activation threshold, Tth(act)otp, causing the

SBC to switch to Overtemp mode

UJA1079_2

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 02 — 27 May 2010

© NXP B.V. 2010. All rights reserved.

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