U630H16P データシートの表示（PDF） - Simtek Corporation
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U630H16P Datasheet PDF : 17 Pages
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U630H16P
Device Operation
The U630H16P has two separate modes of operation:
SRAM mode and nonvolatile mode, determined by the
state of the NE pin. In SRAM mode, the memory opera-
tes as a standard fast static RAM. In nonvolatile mode,
data is transferred from SRAM to EEPROM (the
STORE operation) or from EEPROM to SRAM (the
RECALL operation). In this mode SRAM functions are
disabled.
SRAM READ
The U630H16P performs a READ cycle whenever E
and G are LOW while W and NE are HIGH. The
address specified on pins A0 - A10 determines which of
the 2048 data bytes will be accessed. When the READ
is initiated by an address transition, the outputs will be
valid after a delay of tcR. If the READ is initiated by E or
G, the outputs will be valid at ta(E) or at ta(G), whichever
is later. The data outputs will repeatedly respond to
address changes within the tcR access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W or NE is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and NE is HIGH. The address inputs must be sta-
ble prior to entering the WRITE cycle and must remain
stable until either E or W goes HIGH at the end of the
cycle. The data on pins DQ0 - 7 will be written into the
memory if it is valid tsu(D) before the end of a W control-
led WRITE or tsu(D) before the end of an E controlled
WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Noise Consideration
The U630H16P is a high speed memory and therefore
must have a high frequency bypass capacitor of appro-
ximately 0.1 μF connected between VCC and VSS using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise pro-
blems.
Hardware Nonvolatile STORE
A STORE cycle is performed when NE, E and W are
LOW while G is HIGH. While any sequence to achieve
this state will initiate a STORE, only W initiation and E
initiation are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
STORE cycle, previous nonvolatile data is erased and
the SRAM contents are then programmed into nonvola-
tile elements. Once a STORE cycle is initiated, further
input and output is disabled and the DQ0 - 7 pins are
tristated until the cycle is completed.
If E and G are LOW and W and NE are HIGH at the
end of the cycle, a READ will be performed and the out-
puts will go active, indicating the end of the STORE.
Hardware Nonvolatile RECALL
A RECALL cycle is performed when E, G and NE are
LOW while W is HIGH. Like the STORE cycle, RECALL
is initiated when the last of the three clock-signals goes
to the RECALL state. Once initiated, the RECALL cycle
will take „RECALL Cycle Time“ to complete, during
which all inputs are ignored. When the RECALL com-
pletes, any READ or WRITE state on the input pins will
take effect.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL in no way alters the data in the nonvolatile
cells. The nonvolatile data can be recalled an unlimited
number of times.
Like the STORE cycle, a transition must occur on some
control pins to cause a RECALL, preventing inadver-
tend multi-triggering.
Software Nonvolatile STORE
The U630H16P software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U630H16P implements nonvolatile operation
while remaining compatible with standard 2K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is first performed, followed by
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted and no STORE or RECALL will take
place.
To initiate the STORE cycle the following READ
sequence must be performed:
1. Read address 000 (hex) Valid READ
2. Read address 555 (hex) Valid READ
3. Read address 2AA (hex) Valid READ
4. Read address 7FF (hex) Valid READ
5. Read address 0F0 (hex) Valid READ
6. Read address 70F (hex) Initiate STORE
STK Control #ML0037
14
Rev 1.0
March 31, 2006
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