1400 データシートの表示（PDF） - Linear Technology
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1400 Datasheet PDF : 20 Pages
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LTC1400
APPLICATIO S I FOR ATIO
R1
50Ω
VIN
+
A1
R2
10k
–
R4
100Ω
AIN
LTC1400
R3
10k
FULL-SCALE
ADJUST
GND
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
1400 F10a
Figure 10a. LTC1400 Full-Scale Adjust Circuit
R1
ANALOG 10k
INPUT
0V TO 4.096V
10k
5V
+
R2
A1
10k
–
R9
20Ω
AIN
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
LTC1400
R3
100k
R7
100k
R6
400Ω
5V
R8
10k
OFFSET
ADJUST
1400 F10b
Figure 10b. LTC1400 Offset and Full-Scale Adjust Circuit
R1
ANALOG 10k
INPUT
±2.048V
+
R2
A1
10k –
AIN
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
LTC1400
R3
100k R7
100k
R6
200Ω
5V
R8
20k
OFFSET
ADJUST
–5V
1400 F10c
Figure 10c. LTC1400 Bipolar Offset and Full-Scale Adjust Circuit
error adjustment. Figure 10b shows offset and full-scale
adjustment. Offset error must be adjusted before full-
scale error. Zero offset is achieved by applying 0.5mV
(i.e., 0.5LSB) at the input and adjusting the offset trim
until the LTC1400 output code flickers between 0000
0000 0000 and 0000 0000 0001. For zero full-scale er-
ror, apply an analog input of 4.0945V (FS – 1.5LSB or
last code transition) at the input and adjust R5 until the
LTC1400 output code flickers between 1111 1111 1110
and 1111 1111 1111.
Bipolar Offset and Full-Scale Error Adjustments
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Bipolar offset error adjust-
ment is achieved by applying an input voltage of –0.5mV
(–0.5LSB) to the input in Figure 10c and adjusting the
op amp until the ADC output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjustment,
an input voltage of 2.0465V (FS – 1.5LSBs) is applied to
the input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111.
Board Layout and Bypassing
To obtain the best performance from the LTC1400, a
printed circuit board is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by GND.
High quality tantalum and ceramic bypass capacitors
should be used at the VCC and VREF pins as shown in the
Typical Application on the first page of this data sheet.
For the bipolar mode, a 0.1μF ceramic provides adequate
bypassing for the VSS pin. For optimum performance, a
10μF surface mount AVX capacitor with a 0.1μF ceramic
is recommended for the VCC and VREF pins. The capacitors
must be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible. In
unipolar mode operation, VSS should be isolated from
any noise source before shorting to the GND pin.
1400fa
11
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