CA3318(1997) データシートの表示（PDF） - Intersil
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CA3318 Datasheet PDF : 12 Pages
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CA3318
Absolute Maximum Ratings
DC Supply Voltage Range (VDD or VAA+) . . . . . . . . . . -0.5V to +8V
(Referenced to VSS or VAA- Terminal, Whichever is More Negative)
Input Voltage Range
CE2 and CE1 . . . . . .
Clock, Phase, VREF -,
VCIlNoc,k3,/4PhRaEsFe,,VVRREEFF+-,
...
11//24
...
...
Ref
Ref
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. VAA- -0.5V to VDD
VAA- -0.5V to VAA+
. VSS- -0.5V to VDD
. VAA- -0.5V to VAA-
+
+
+
+
0.5V
0.5V
0.5V
7.5V
Output Voltage Range, . . . . . . . . . . . . . . . VSS - 0.5V to VDD + 0.5V
Bits 1-8, Overflow (Outputs Off)
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Clock, Phase, CE1, CE2, VIN, Bits 1-8, Overflow
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . . . .
60
22
PDIP Package . . . . . . . . . . . . . . . . . . . . .
60
N/A
SOIC Package . . . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 265oC
(SOIC - Lead Tips Only)
Operating Conditions
Operating Voltage Range (VDD or VAA+) . . . 4V (Min) to 7.5V (Max)
Recommended VAA+ Operating Range . . . . . . . . . . . . . . . VDD ±1V
Recommended VAA- Operating Range
Operating Temperature Range (TA) . . .
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-.4.0.o.CVtSoS85±1oCV
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications At 25oC, VAA+ = VDD = 5V, VREF+ = 6.4V, VREF - = VAA- = VSS, CLK = 15MHz,
All Reference Points Adjusted, Unless Otherwise Specified
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error
Differential Linearity Error
Offset Error, Unadjusted
Gain Error Unadjusted
DYNAMIC CHARACTERISTICS
Maximum Input Bandwidth
Maximum Conversion Speed
Signal to Noise Ratio (SNR)
= R-R----M-M----S-S---S-N----i-o-g---in--s--a-e---l
TEST CONDITIONS
VIN = VREF- + 1/2 LSB
VIN = VREF+ - 1/2 LSB
(Note 1) CA3318
CLK = Square Wave
fS = 15MHz, fIN = 100kHz
fS = 15MHz, fIN = 4MHz
MIN
TYP
MAX
UNITS
8
-
-
Bits
-
-
± 1.5
LSB
-
-
+1, -0.8
LSB
-0.5
4.5
6.4
LSB
-1.5
0
1.5
LSB
2.5
5.0
15
17
-
47
-
43
-
MHz
-
MSPS
-
dB
-
dB
Signal to Noise Ratio (SINAD)
= R-----M-----S----RN-----Mo----i-S-s---Se----+-i-g--D--n--i-s-a--t--lo---r---t-i-o----n-
fS = 15MHz, fIN = 100kHz
fS = 15MHz, fIN = 4MHz
-
45
-
dB
-
35
-
dB
Total Harmonic Distortion, THD
Effective Number of Bits (ENOB)
Differential Gain Error
Differential Phase Error
ANALOG INPUTS
Full Scale Range, VIN and (VREF+) - (VREF-)
Input Capacitance, VIN
Input Current, VIN, (See Text)
REFERENCE INPUTS
Ladder Impedance
fS = 15MHz, fIN = 100kHz
fS = 15MHz, fIN = 4MHz
fS = 15MHz, fIN = 100kHz
fS = 15MHz, fIN = 4MHz
Unadjusted
Unadjusted
Notes 2, 4
VIN = 5V, VREF+ = 5V
-
-46
-
dBc
-
-36
-
dBc
-
7.2
-
Bits
-
5.5
-
Bits
-
2
-
%
-
1
-
%
4
-
7
V
-
30
-
pF
-
-
3.5
mA
270
500
800
Ω
4-11
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