IDT61298SA(2007) データシートの表示（PDF） - Integrated Device Technology

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IDT61298SA
(Rev.:2007)

CMOS Static RAM 256K (64K x 4-Bit)

Integrated Device Technology 

IDT61298SA

CMOS Static RAM 256K (64K x 4-Bit)

Timing Waveform of Read Cycle No. 1(1)

t RC

ADDRESS

OE

CS

DATA OUT

t AA

t OE

t OLZ (5)

t ACS

t CLZ (5)

Commercial Temperature Range

t OH

t OHZ (5)

t CHZ (5)

DATA VALID

,

2971 drw 05

Timing Waveform of Read Cycle No. 2(1,2,4)

t RC

ADDRESS

DATAOUT

t AA

t OH

Timing Waveform of Read Cycle No. 3(1,3,4)

CS

DATAOUT

VCC ICC

SUPPLY

CURRENT ISB

t ACS

t CLZ (5)

t PU

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continuously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

tOH

DATA VALID

, 2971 drw 06

DATA VALID

t CHZ (5)

t PD

, 2971 drw 07

6.452

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