MC14043BFELG(2013) データシートの表示（PDF） - ON Semiconductor
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MC14043BFELG Datasheet PDF : 7 Pages
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MC14043B, MC14044B
CMOS MSI
Quad R−S Latches
The MC14043B and MC14044B quad R−S latches are constructed
with MOS P−Channel and N−Channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three−state
buffers having a common enable input. The outputs are enabled with a
logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Features
• Double Diode Input Protection
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg
Storage Temperature Range
TL
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2013
1
April, 2013 − Rev. 9
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 16
P SUFFIX
CASE 648
1
MC140xxBCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
16
140xxBG
AWLYWW
1
SOEIAJ−16
F SUFFIX
CASE 966
16
MC14043B
ALYWG
1
xx
A
WL, L
YY, Y
WW, W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
MC14043B/D
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