MAX154 データシートの表示（PDF） - Maxim Integrated
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MAX154 Datasheet PDF : 12 Pages
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CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, VREF+ = +5V, VREF- = GND, MODE 0, TA = TMIN to TMAX, unless otherwise noted).
PARAMETER
LOGIC OUTPUTS
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output High Voltage
VOH DB0-DB7, INT; IOUT = -360µA
4.0
V
Output Low Voltage
VOL
DB0-DB7, INT; RDY
IOUT = 1.6mA
IOUT = 2.6mA
0.4
V
0.4
Three-State Output Current
DB0-DB7, RDY; VOUT = 0V to VDD
±3
µA
Output Capacitance (Note 4)
COUT
5
8
pF
POWER-SUPPLY
Supply Voltage
VDD 5V ±5% for specified performance
4.75
5.25
V
Supply Current
IDD CS = RD = 2.4V
15
mA
Power Dissipation
25
75
mW
Power-Supply Sensitivity
PSS VDD = ±5%
±1/16 ±1/4 LSB
Note 1: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 2: Specified with no external load unless otherwise noted.
Note 3: Temperature drift is defined as change in output voltage from +25°C to TMIN or TMAX divided by (25 - TMIN) or (TMAX - 25).
Note 4: Guaranteed by design.
TIMING CHARACTERISTICS (Note 5)
(VDD = +5V, VREF+ = +5V, VREF- = GND, MODE 0, TA = TMIN to TMAX, unless otherwise noted).
PARAMETER
CS to RD Setup Time
CS to RD Hold Time
Multiplexer Address
Setup Time
SYMBOL
tCSS
tCSH
tAS
CONDITIONS
TA = +25°C
MIN TYP MAX
0
0
MAX15_C/E
MIN MAX
0
0
0
0
MAX15_M
MIN MAX
0
0
UNITS
ns
ns
0
ns
Multiplexer Address
Hold Time
tAH
30
35
40
ns
CS to RDY Delay
tRDY CL = 50pF, RL = 5kΩ
30 40
60
60
ns
Conversion Time (Mode 0)
tCRD
1.6 2.0
2.4
2.8
µs
Data Access Time After RD
tACC1 (Note 6)
85
110
120 ns
Data Access Time
After INT, Mode 0
tACC2 (Note 6)
20 50
60
70
ns
RD to INT Delay (Mode 1)
Data Hold Time
Delay Time
Between Conversions
tINTH
tDH
tP
CL = 50pF
(Note 7)
40 75
100
100 ns
60
70
70
ns
500
500
600
ns
RD Pulse Width (Mode 1)
tRD
60
600 80
500
80
400 ns
Note 5: All input control signals are specified with tR = tF = 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level.
Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
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