IDT723613L30PF データシートの表示（PDF） - Integrated Device Technology

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IDT723613L30PF

CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36

COMMERCIAL TEMPERATURE RANGES

BE SIZ1 SIZ0

H HL

B35 B27

B35 B27

B26 B18

B26 B18

B17 B9

B8 B0

D 1st: Read from FIFO

B17 B9

B8 B0

C 2nd: Read from FIFO

A35 A27

B35 B27

A26 A18

B26 B18

A17 A9

B17 B9

A8 A0

B 3rd: Read from FIFO

B8 B0

A 4th: Read from FIFO

(d) BYTE SIZE — LITTLE ENDIAN

3145 drw fig 01a

Figure 1. Dynamic Bus Sizing (continued)

Byte arrangement is chosen by the port B swap select

(SW0, SW1) inputs on a CLKB rising edge that reads a new

long word from the FIFO. The byte order chosen on the first

byte or first word of a new long word read from the FIFO is

maintained until the entire long word is transferred, regard-

less of the SW0 and SW1 states during subsequent reads.

Figure 3 is an example of the byte-order swapping available

for long word reads. Performing a byte swap and bus-size

simulationeously for a FIFO read first rearranges the bytes as

shown in Figure 3, then outputs the bytes as shown in Figure

1.

PORT-B MAIL REGISTER ACCESS

In addition to selecting port B bus sizes for FIFO

reads, the port B bus size select (SIZ0, SIZ1) inputs also

access the mail registers. When both SIZ0 and SIZ1 are

HIGH, the mail1 register is accessed for a port B long-word

read and the mail2 register is accessed for a port B long-word

write. The mail register is accessed immediately and any

bus-sizing operation that can be underway is unaffected by

the mail register access. After the mail register access is

complete, the previous FIFO access can resume in the next

CLKB

G1 MUX

SIZ0

SIZ1

BE

••

1

•

SIZ0 Q

1

D

Q

SIZ1 Q

• • BE Q

3145 drw fig 02

Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register

13

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