CDP1826C
CLEAR WAIT
ADDR BUS
TPA
ADDR BUS
TPA
N0 - N2 MRD
TPB
Q
ROM
RAM
CDP1826C
CPU
SCO SCI
CDP1800
I/O
SERIES
INTERRUPT
MRD
CEO
MRD
MWR
DMA - IN DMA OUT
EF1 - EF4
DATA
CONTROL
8-BIT BIDIRECTIONAL DATA BUS
FIGURE 1. TYPICAL CDP1802 MICROPROCESSOR SYSTEM
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