HI5813(2001) データシートの表示（PDF） - Intersil

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HI5813
(Rev.:2001)

CMOS 3.3V, 30 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold

Intersil 

HI5813

Theory of Operation

HI5813 is a CMOS 12-Bit, Analog-to-Digital Converter that

uses capacitor charge balancing to successively

approximate the analog input. A binary weighted capacitor

network forms the A/D heart of the device. See the block

diagram for the HI5813.

The capacitor network has a common node which is

connected to a comparator. The second terminal of each

capacitor is individually switchable to the input, VREF+ or

VREF -.

During the first three clock periods of a conversion cycle, the

switchable end of every capacitor is connected to the input

and the comparator is being auto balanced at the capacitor

common node.

During the fourth period, all capacitors are disconnected

from the input; the one representing the MSB (D11) is

connected to the VREF+ terminal; and the remaining

capacitors to VREF -. The capacitor common node, after the

charges balance out, will indicate whether the input was

above 1/2 of (VREF+ - VREF -). At the end of the fourth

period, the comparator output is stored and the MSB

capacitor is either left connected to VREF+ (if the comparator

cwoamsphaigrihs)oonrtorebtuernaet deittoheVrR3E/4F

-. This allows the next

or 1/4 of (VREF+ - VREF

-).

At the end of periods 5 through 14, capacitors representing

D10 through D1 are tested, the result stored, and each

capacitor either left at VREF+ or at VREF -.

At the end of the 15th period, when the LSB (D0) capacitor is

tested, (D0) and all the previous results are shifted to the

output registers and drivers. The capacitors are reconnected

to the input, the comparator returns to the balance state, and

the data ready output goes active. The conversion cycle is

now complete.

Analog Input

The analog input pin is a predominately capacitive load that

changes between the track and hold periods of the

conversion cycle. During hold, clock period 4 through 15, the

input loading is leakage and stray capacitance, typically less

than 5µA and 20pF.

At the start of input tracking, clock period 1, some charge is

dumped back to the input pin. The input source must have

low enough impedance to dissipate the current spike by the

end of the tracking period. The amount of charge is

dependent on supply and input voltages. The average

current is also proportional to clock frequency.

As long as these current spikes settle completely by end of

the signal acquisition period, converter accuracy will be

preserved. The analog input is tracked for 3 clock cycles.

With a clock of 500kHz the track period is 6µs.

A simplified analog input model is presented in Figure 12.

During tracking, the A/D input (VIN) typically appears as a

380pF capacitor being charged through a 420Ω internal

switch resistance. The time constant is 160ns. To charge this

capacitor from an external “zero Ω” source to 0.5 LSB

(1/8192), the charging time must be at least 9 time constants

or 1.4µs. The maximum source impedance (RSOURCE Max)

for a 6µs acquisition time settling to within 0.5 LSB is 1.3kΩ.

If the clock frequency was slower, or the converter was not

restarted immediately (causing a longer sample time), a

higher source impedance could be tolerated.

VIN

RSW ≈ 420Ω

RSOURCE

CSAMPLE ≈ 380pF

RSOURCE

(MAX)

=

-tACQ

CSAMPLE ln [2-(N

+

1-)]RSW

FIGURE 12. ANALOG INPUT MODEL IN TRACK MODE

Reference Input

The reference input VREF+ should be driven from a low

impedance source and be well decoupled.

Current spikes are generated on the reference pin during

each bit test of the successive approximation part of the

conversion cycle as the charge balancing capacitors are

switched between VREF - and VREF+ (clock periods 5 - 14).

These current spikes must settle completely during each bit

test of the conversion to not degrade the accuracy of the

converter. Therefore VREF+ and VREF - should be well

bypassed. Reference input VREF - is normally connected

directly to the analog ground plane. If VREF- is biased for

nulling the converters offset it must be stable during the

conversion cycle.

Full Scale and Offset Adjustment

In many applications the accuracy of the HI5813 would be

sufficient without any adjustments. In applications where

accuracy is of utmost importance full scale and offset errors

may be adjusted to zero.

The VREF+ and VREF - pins reference the two ends of the

analog input range and may be used for offset and full scale

adjustments. In a typical system the VREF - might be

returned to a clean ground, and the offset adjustment done

on an input amplifier. VREF+ would then be adjusted to null

out the full scale error. When this is not possible, the VREF -

input can be adjusted to null the offset error, however, VREF -

must be well decoupled.

Full scale and offset error can also be adjusted to zero in the

signal conditioning amplifier driving the analog input (VIN).

Control Signal

The HI5813 may be synchronized from an external source

by using the STRT (Start Conversion) input to initiate

conversion, or if STRT is tied low, may be allowed to free

run. Each conversion cycle takes 15 clock periods.

The input is tracked from clock period 1 through period 3,

then disconnected as the successive approximation takes

place. After the start of the next period 1 (specified by tD

data), the output is updated.

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