AD9856 データシートの表示（PDF） - Analog Devices

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AD9856

CMOS 200 MHz Quadrature Digital Upconverter

Analog Devices 

AD9856

Table 4. Functional Block Mode Descriptions

Functional Block Mode Description

Operating Modes

1. Complex quadrature modulator mode.

2. Single-tone output mode.

Input Data Format

Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is 12-bit, twos complement. Complex

I/Q symbol component data is required to be at least 2× oversampled, depending upon configuration.

Input Sample Rate Up to 50 Msamples/sec @ 200 MHz SYSCLK rate.

Input Reference

Clock Frequency

For DC to 80 MHz AOUT operation (200 MHz SYSCLK rate) with REFCLK multiplier enabled: 10 MHz to50 MHz,

programmable via control bus; with REFCLK multiplier disabled: 200 MHz.

Note: For optimum data synchronization, the AD9856 reference clock and the input data clock should be derived

from the same clock source.

Internal Reference

Clock Multiplier

Programmable in integer steps over the range of 4× to 20×. Can be disabled (effective REFCLK multiplier = 1) via

control bus. Output of REFCLK multiplier = SYSCLK rate, which is the internal clock rate applied to the DDS and DAC

function.

Profile Select

Four pin-selectable, preprogrammed formats. Available for modulation and single-tone operating modes.

Interpolating Range Fixed 4×, selectable 2×, and selectable 2× to 63× range.

Half-Band Filters

Interpolating filters that provide upsampling and reduce the effects of the CIC passband roll-off characteristics.

TxENABLE Function– When burst mode is enabled via the control bus, the rising edge of the applied TxENABLE pulse should be

Burst Mode

coincident with, and frame, the input data packet. This establishes data sampling synchronization.

TxENABLE Function– When continuous mode is enabled via the control bus, the TxENABLE pin becomes an I/Q control line. A Logic 1

Continuous Mode on TxENABLE indicates I data is being presented to the AD9856. A Logic 0 on TxENABLE indicates Q data is being

presented to the AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sampling capability.

Inverse SINC Filter Precompensates for SIN(x)/x roll-off of DAC; user bypassable.

I/Q Channel Invert [I ×Cos(ωt) + Q ×Sin(ωt)] or [I ×Cos(ωt) − Q ×Sin(ωt)] (default), configurable via control bus, per profile.

Full Sleep Mode

Power dissipation reduced to less than 6 mW when full sleep mode is active; programmable via the control bus.

Rev. C | Page 7 of 36

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