TC58DVM92A1FT00 データシートの表示（PDF） - Toshiba

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TC58DVM92A1FT00

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Toshiba 

TC58DVM92A1FT00

Internal addressing in relation with the Districts

To use Multi Block Erase operation, the internal addressing should be conscious in relation with the Districts.

x The device consists of 4 Districts.

x Each District consists from 1024 erase blocks.

x The allocation rule is follows.

District 0: Block 0, Block 4, Block 8, Block 12,

···.., Block 4092

District 1: Block 1, Block 5, Block 9, Block 13,

···.., Block 4093

District 2: Block 2, Block 6, Block 10, Block 14,

···.., Block 4094

District 3: Block 3, Block 7, Block 11, Block 15,

···.., Block 4095

Address input restriction for the Multi Block Erase operation

In selecting the blocks for the Multi Block Erase operation, following is the restriction and acceptance.

(Restriction)

Maximum one block should be selected from each District.

(Acceptance)

There is no order limitation of the District for the address input.

Any number of the Districts can be select for the erase operation.

So, for example, following operation are in acceptance.

Example 1 : (60) [District 2] (60) [District 0] (60) [District 1] (D0)

Example 2 : (60) [District 0] (60) [District 1] (60) [District 2] (60) [District 3]

(D0)

It requires no mutual address relation between the selected blocks from each District.

2003-01-10 31/44

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