SY100EL34LZG データシートの表示（PDF） - Micrel

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コンポーネント説明

一致するリスト

SY100EL34LZG

5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip

Micrel 

Micrel, Inc.

Timing Diagram

Precision Edge®

SY10EL34/L

SY100EL34/L

The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal

dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are

unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had

the EN signal not been asserted.

December 2011

7

M9999-120611-I

hbwhelp@micrel.com or (408) 955-1690

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