STK16C88-3 データシートの表示（PDF） - Cypress Semiconductor
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STK16C88-3 Datasheet PDF : 14 Pages
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STK16C88-3
Table 3. SRAM Write Cycle
Parameter
Cypress
Parameter
Alt
tWC
tAVAV
tPWE
tWLWH, tWLEH
tSCE
tELWH, tELEH
tSD
tDVWH, tDVEH
tHD
tWHDX, tEHDX
tAW
tAVWH, tAVEH
tSA
tAVWL, tAVEL
tHA
tHZWE [7,8]
tLZWE [7]
tWHAX, tEHAX
tWLQZ
tWHQX
Switching Waveforms
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Figure 7. SRAM Write Cycle 1: WE Controlled [9]
ADDRESS
CE
WE
tWC
tSCE
tHA
tAW
tSA
tPWE
35 ns
Unit
Min
Max
35
ns
25
ns
25
ns
12
ns
0
ns
25
ns
0
ns
0
ns
13
ns
5
ns
DATA IN
DATA OUT
ADDRESS
PREVIOUS DATA
tHZWE
tSD
tHD
DATA VALID
HIGH IMPEDANCE
Figure 8. SRAM Write Cycle 2: CE Controlled [9]
tWC
tLZWE
tSA
tSCE
tHA
CE
WE
DATA IN
tAW
tPWE
tSD
tHD
DATA VALID
DATA OUT
HIGH IMPEDANCE
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9. CE or WE must be greater than VIH during address transitions.
Document Number: 001-50594 Rev. **
Page 9 of 14
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