STE100A データシートの表示（PDF） - STMicroelectronics

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STE100A

PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STMicroelectronics 

STE10/100A

Functional description

3.4

Receive scheme and receive early interrupt scheme

The following figure shows the difference of timing without early interrupt and with early

interrupt.

Figure 12. Receive data flow (without early interrupt and with early interrupt)

Incoming packet

Receive FIFO operation

FIFO-to-host memory operation

Interrupt

Driver read header

Higher layer process

Driver read the rest data

Receive early interrupt

Driver read header (early)

Higher layer process (early)

Driver read the rest data

Finish time

Finish time

Time

: without early interrupt

: with early interrupt

Figure 13. Detailed receive early interrupt flow

The size of 1st

descriptor is

programmed as the

header size in

advance

FIFO-to-host memory operation

1st

descriptor

full

2 descriptor

Issue 2

interrupt at end

of packet

PC00357

Receive early interrupt

Driver read header (early)

Higher layer process (early)

Driver read the rest data

Time

Finish

PC00358

19/82

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