STE100A データシートの表示（PDF） - STMicroelectronics

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STE100A

PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STMicroelectronics 

STE10/100A

3.2.2

Descriptor management

OWN bit = 1, ready for network side access

OWN bit = 0, ready for host side access

Transmit descriptors

Figure 7. Transmit descriptor management

Descriptor ring

Ext packet to be transmitted

Own bit=1,

packet 1 and packet 2

are ready to transmit

0

Length 2 Length1

Buffer 1 pointer

Buffer 2 pointer

1

Packet1

1

Packet1

Empty descriptor pointer

1

Packet2

0

·

·

·

End of ring 0

Functional description

Data buffer

Data

Data

PC00352

15/82

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