ST6381B4/XXX データシートの表示（PDF） - STMicroelectronics

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ST6381B4/XXX

8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING

STMicroelectronics 

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

1.2 PIN DESCRIPTION

VDD and VSS. Power is supplied to the MCU using

these two pins. VDD is power and VSS is the

ground connection.

OSCin, OSCout. These pins are internally con-

nected to the on-chip oscillator circuit. A quartz

crystal or a ceramic resonator can be connected

between these two pins in order to allow the cor-

rect operation of the MCU with various stability/

cost trade-offs. The OSCin pin is the input pin, the

OSCout pin is the output pin.

RESET. The active low RESET pin is used to start

the microcontroller to the beginning of its program.

Additionally the quartz crystal oscillator will be dis-

abled when the RESET pin is low to reduce power

consumption during reset phase.

TEST. The TEST pin must be held at VSS for nor-

mal operation.

PA0-PA7. These 8 lines are organized as one I/O

port (A). Each line may be configured as either an

input with or without pull-up resistor or as an out-

put under software control of the data direction

register. Pins PA4 to PA7 are configured as open-

drain outputs (12V drive). On PA4-PA7 pins the in-

put pull-up option is not available while PA6 and

PA7 have additional current driving capability

(25mA, VOL:1V). PA0 to PA3 pins are configured

as push-pull.

PB0-PB6. These 7 lines are organized as one I/O

port (B). Each line may be configured as either an

input with or without internal pull-up resistor or as

an output under software control of the data direc-

tion register. In addition any pin can be configured

by software as the input to the Analog to Digital

converter. In this case only one pin should be con-

figured at any time to avoid conflicts.

PC0-PC7. These 8 lines are organized as one I/O

port (C). Each line may be configured as either an

input with or without internal pull-up resistor or as

an output under software control of the data direc-

tion register. Pins PC0 to PC3 are configured as

open-drain (5V drive) in output mode while PC4 to

PC7 are open-drain with 12V drive and the input

pull-up options does not exist on these four pins.

PC0, PC1 and PC3 lines when in output mode are

“ANDed” with the SPI control signals and are all

open-drain. PC0 is connected to the SPI clock sig-

nal (SCL), PC1 with the SPI data signal (SDA)

while PC3 is connected with SPI enable signal

(SEN, used in S-BUS protocol). Pin PC4 and PC6

can also be inputs to software programmable edge

sensitive latches which can generate interrupts;

PC4 can be connected to Power Interrupt while

PC6 can be connected to the IRIN/NMI interrupt

line.

DA0-DA5. These pins are the six PWM D/A out-

puts of the 6-bit on-chip D/A converters. These

lines have open-drain outputs with 12V drive. The

output repetition rate is 31.25KHz (with 8MHz

clock).

OSDOSCin, OSDOSCout. These are the On

Screen Display oscillator terminals. An oscillation

capacitor and coil network have to be connected to

provide the right signal to the OSD.

HSYNC, VSYNC. These are the horizontal and

vertical synchronization pins. The active polarity of

these pins to the OSD macrocell can be selected

by the user as ROM mask option. If the device is

specified to have negative logic inputs, then these

signals are low the OSD oscillator stops. If the de-

vice is specified to have positive logic inputs, then

when these signals are high the OSD oscillator

stops. VSYNC is also connected to the VSYNC in-

terrupt.

R, G, B, BLANK. Outputs from the OSD. R, G and

B are the color outputs while BLANK is the blank-

ing output. All outputs are push-pull.

VS. This is the output pin of the on-chip 14-bit volt-

age synthesis tuning cell (VS). The tuning signal

present at this pin gives an approximate resolution

of 40KHz per step over the UHF band. This line is

a push-pull output with standard drive.

7/82

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