SST89E52RC データシートの表示（PDF） - Silicon Storage Technology

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SST89E52RC

FlashFlex MCU

Silicon Storage Technology 

FlashFlex MCU

SST89E52RC / SST89E54RC

2.1 Pin Descriptions

Data Sheet

TABLE 2-1: Pin Descriptions (1 of 2)

Symbol

Type1

Name and Functions

P0[7:0]

I/O

Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can

sink several LS TTL inputs. Port 0 pins that have ‘1’s written to them float, and in this state

can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and

data bus during accesses to external code and data memory. In this application, it uses

strong internal pull-ups when transitioning to ‘1’s. Port 0 also receives the code bytes during

the external host mode programming, and outputs the code bytes during the external host

mode verification. External pull-ups are required during program verification or as a general

purpose I/O port.

P1[7:0]

I/O with internal

pull-up

Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers

can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when ‘1’s are writ-

ten to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally

pulled low will source current (IIL, see Table 12-6) because of the internal pull-ups. P1[5, 6, 7]

have high current drive of 16 mA. Port 1 also receives the low-order address byte during the

external host mode programming and verification.

P1[0]

I/O

T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2

P1[1]

I

T2EX: Timer/Counter 2 capture/reload trigger and direction control

P1[2]

I/O

GPIO

P1[3]

I/O

GPIO

P1[4]

I/O

GPIO

P1[5]

I/O

GPIO

P1[6]

I/O

GPIO

P1[7]

I/O

GPIO

P2[7:0]

I/O

with internal

pull-up

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled

high by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this

state. As inputs, Port 2 pins that are externally pulled low will source current (IIL, see Table

12-6) because of the internal pull-ups. Port 2 sends the high-order address byte during

fetches from external program memory and during accesses to external Data Memory that

use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups when

transitioning to ‘1’s. Port 2 also receives the high-order address byte during the external host

mode programming and verification.

P3[7:0]

I/O

with internal

pull-up

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers

can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when ‘1’s are writ-

ten to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally

pulled low will source current (IIL, see Table 12-6) because of the internal pull-ups. Port 3 also

receives the high-order address byte during the external host mode programming and verifi-

cation.

P3[0]

I

RXD: Universal Asynchronous Receiver/Transmitter (UART) - Receive input

P3[1]

O

TXD: UART - Transmit output

P3[2]

I

INT0#: External Interrupt 0 Input

P3[3]

I

INT1#: External Interrupt 1 Input

P3[4]

I

T0: External count input to Timer/Counter 0

P3[5]

I

T1: External count input to Timer/Counter 1

P3[6]

O

WR#: External Data Memory Write strobe

P3[7]

O

RD#: External Data Memory Read strobe

©2007 Silicon Storage Technology, Inc.

7

S71259-04-000

1/07

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