SST34HF1681 データシートの表示（PDF） - Silicon Storage Technology
部品番号
コンポーネント説明
一致するリスト
SST34HF1681 Datasheet PDF : 30 Pages
| |||
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
SRAM bank enable signal, BES1# and BES2, selects the
SRAM bank. The flash memory bank enable signal, BEF#,
has to be used with Software Data Protection (SDP) com-
mand sequence when controlling the Erase and Program
operations in the flash memory bank. The memory banks
are superimposed in the same memory address space
where they share common address lines, data lines, WE#
and OE# which minimize power consumption and area.
Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the SST34HF1681 are
offered in both commercial and extended temperatures
and a small footprint package to meet board space con-
straint requirements.
Advance Specifications
CONCURRENT READ/WRITE STATE TABLE
Flash
Bank 1
Bank 2
Read
Write
Write
Read
Write
No Operation
No Operation
Write
Write
No Operation
No Operation
Write
SRAM
No Operation
No Operation
Read
Read
Write
Write
Note: For the purposes of this table, write means to Block-, Sector,
or Chip-Erase, or Word-Program as applicable to the
appropriate bank.
Device Operation
The SST34HF1681 uses BES1#, BES2 and BEF# to con-
trol operation of either the flash or the SRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the SRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time. If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
SRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to VIHC (Logic High) or
when BEF# is high and BES2 is low.
Concurrent Read/Write Operation
Dual bank architecture of SST34HF1681 devices allows
the Concurrent Read/Write operation whereby the user
can read from one bank while program or erase in the
other bank. This operation can be used when the user
needs to read system code in one bank while updating
data in the other bank. See Figure 1 for Dual-Bank Memory
Organization.
Flash Read Operation
The Read operation of the SST34HF1681 is controlled by
BEF# and OE#, both have to be low for the system to
obtain data from the outputs. BEF# is used for device
selection. When BEF# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either BEF# or OE# is
high. Refer to the Read cycle timing diagram for further
details (Figure 6).
Flash Word-Program Operation
The SST34HF1681 are programmed on a word-by-word
basis. Before Program operations, the memory must be
erased first. The Program operation consists of three steps.
The first step is the three-byte load sequence for Software
Data Protection. The second step is to load word address
and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either BEF# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either BEF# or WE#, whichever occurs first.
The third step is the internal Program operation which is ini-
tiated after the rising edge of the fourth WE# or BEF#,
whichever occurs first. The Program operation, once initi-
ated, will be completed typically within 10 µs. See Figures 7
and 8 for WE# and BEF# controlled Program operation tim-
ing diagrams and Figure 21 for flowcharts. During the Pro-
gram operation, the only valid reads are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
©2001 Silicon Storage Technology, Inc.
2
S71214-00-000 12/01 561
Share Link: 