SST31LF041 データシートの表示（PDF） - Silicon Storage Technology
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SST31LF041 Datasheet PDF : 26 Pages
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4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory
SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A
Data Sheet
which returns the device to the Read operation. Please
note that the software-reset command is ignored during an
internal Program or Erase operation. See Table 4 for soft-
ware command codes, Figure 13 for timing waveform and
Figure 19 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
SRAM
AMS - A0
BES#
BEF#
OE#
WE#
Control Logic
Address Buffers
& Latches
AMS = Most Significant Address
SuperFlash
Memory
I/O Buffers
DQ7 - DQ0
349 ILL B1.6
A16
1
A15
2
A14
3
A13
4
A12
5
A11
6
A9
7
A8
8
WE#
9
NC
10
BES#
11
NC
12
A18
13
A7
14
A6
15
A5
16
A4
17
A3
18
A2
19
A1
20
Standard Pinout
Top View
Die Up
40
A17
39
VSS
38
NC
37
NC
36
A10
35
DQ7
34
DQ6
33
DQ5
32
DQ4
31
VDD
30
VDD
29
NC
28
DQ3
27
DQ2
26
DQ1
25
DQ0
24
OE#
23
VSS
22
BEF#
21
A0
349 ILL F01.2
FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP (10MM X 14MM) - SSTLF041/043
©2001 Silicon Storage Technology, Inc.
5
S71107-03-000 5/01 349
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