SSD1332 データシートの表示（PDF） - Solomon Systech

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SSD1332

OLED/PLED Segment/Common Driver with Controller

Solomon Systech  

FUNCTIONAL BLOCK DESCRIPTIONS

Oscillator Circuit and Display Time Generator

Internal

Oscillator

CL

M CLK

U

X

Divider

DCLK

Internal

Display

Clock

Figure 3 - Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry (Figure 3). The oscillator generates the clock for the

Display Timing Generator.

Reset Circuit

When RES# input is low, the chip is initialized with the following status:

1. Display is OFF

2. 64 mux Display Mode

3. Normal segment and display data column address and row address mapping (SEG0 mapped to

address 00H and COM0 mapped to address 00H)

4. Shift register data clear in serial interface

5. Display start line is set at display RAM address 0

6. Column address counter is set at 0

7. Normal scan direction of the COM outputs

8. Master contrast control register is set at 16H

9. Individual contrast control registers of color A, B, and C are set at 80H

Command Decoder and Command Interface

This module determines whether the input data is interpreted as data or command. Data is interpreted

based upon the input of the D/C# pin.

If D/C# pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at D7-D0

is interpreted as a Command and it will be decoded and be written to the corresponding command

register.

9

SSD1332

Rev 0.23

08/2003

SOLOMON

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