M4640-19 データシートの表示（PDF） - Conexant Systems

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M4640-19

Baseband Processor for GSM Applications

Conexant Systems 

Baseband Processor

M46

Table 5. Clock Control Register Functions

Bit

Block Controlled

15

IrDA / Escape Sequence

14

DSP

13

Reserved

12

DMA Controlled

11

Autobaud

10

SDS Port

9

Debug Port

8

PTGB

Bit

Block Controlled

7

PTGA

6

CRC

5

Timer B

4

PWM

3

SIM

2

Reserved

1

SIU

0

ARM Core

System Clock

÷P

Input

Clock

PLL

÷M

Figure 5. PLL Functional Block Diagram

DSP Clock

(Input Clock x N)

ARM Clock

C855

Interrupt Pending Register. All interrupt sources are latched

into the Interrupt Pending Register. When an interrupt is latched

into this register the bit will remain set to “1” until the interrupt

source has disappeared and the bit is cleared by the ARM. The

source of each of the bits in the register is specified in Table 6.

Interrupt Select Register. Every enabled interrupt source can

generate either an FIQ or IRQ interrupt to the ARM core. The

Interrupt Select Register contains a bit for each possible

interrupt source. If the associated bit is set to “1,” an FIQ

interrupt is generated when an interrupt occurs and the interrupt

is enabled. Conversely, if the bit is set to “0,” an IRQ interrupt is

generated when an interrupt occurs and the interrupt is enabled.

The Interrupt Select Register bits have the same mapping to the

interrupt sources as the Interrupt Pending Register (see

Table 6).

Interrupt Enable Register. The Interrupt Enable Register

contains a corresponding bit for each possible interrupt source.

If the bit is set to “1,” and an interrupt occurs, an interrupt is sent

to the ARM. Either an FIQ or IRQ interrupt is generated

depending on the status of the associated interrupt bit in the

Interrupt Select Register. If the bit is set to “0,” the interrupt is

disabled.

The Interrupt Enable Register bits have the same mapping to

the interrupt sources as the Interrupt Pending Register (see

Table 6).

External Interrupt Polarity Register. The polarity of all external

interrupts is selected by writing to the appropriate bit in the

Interrupt Polarity Register. If the bit is set to “1,” an interrupt is

generated on the falling edge of the signal. If the bit is set to “0,”

the rising edge of the signal is the interrupting edge.

Care must be taken since the act of altering the bit could result

in the generation of an interrupt edge. This potential hazard can

be avoided by using software to disable the interrupt source

when the polarity bit is changed.

The External Interrupt Polarity Register bits have the same

mapping to the interrupt sources as the Interrupt Pending

Register (see Table 6). For internally generated interrupts, the

associated bits in this register are unused.

FIQ Interrupt Register. The FIQ Interrupt Register contains bits

for all the possible interrupt sources. The FIQ Interrupt Register

bits have the same mapping to the interrupt sources as the

Interrupt Pending Register (see Table 6). If a bit for a particular

interrupt is set to 1, the following conditions apply to that

interrupt:

• The interrupt has occurred

• The interrupt is enabled

• The interrupt is set to generate an FIQ interrupt

If the bit is set to 0, at least one of the conditions listed above is

not met.

100779C

Conexant

Proprietary Information and Specifications are Subject to Change

15

June 14, 2000

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