GM16C550 データシートの表示（PDF） - Hynix Semiconductor
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GM16C550 Datasheet PDF : 22 Pages
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Registers
The system programmer may be Access any of the
UART registers summarized in Table II via the CPU.
These registers control UART operations including
transmission and reception of data. Each register bit in
Table II has its name and reset state shown.
LINE CONTROL REGISTER
The system programmer specifies the format of the
asynchronous data communications exchange and set the
Divisor Latch Access bit via the Line Control Register
(LCR). The programmer can also read the contents of the
Line Control Register. The read capability simplifies
system programming and eliminates the need for
separate storage in system memory of the LCR. Details
on each bit follow:
Bit 0 and 1: These two bits specify the number of bits
in each transmitted or received serial character. The
encoding of bits 0 and 1 is as follows.
Bit 1
Bit 0
Character Length
0
0
5 Bits
0
1
6 Bits
1
0
7 Bits
1
1
8 Bits
Bit 2: This bit specifies the number of Stop bits
transmitted and received in each serial character. If bit 2
is a logic 0, one Stop bit is generated in the transmitted
data. If Bit 2 is a logic 1 when a 5-bit word length is
selected via bits 0 and 1, one and a half Stop bits are
generated. If bit 2 is a logic 1 When either a 6-, 7-, or 8-
bit word length is selected, two Stop bit are generated.
The Receiver checks the first Stop bit only, regardless of
the number of Stop bit selected.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic
1, a Parity bit is generated (transmit data) or checked
(receive data) between the last data word bit and Stop bit of
the serial data. (The Parity bit is used to produce an even or
odd number of 1s when the data word bits and the Parity bit
Typical Clock Circuits
EXTERNAL
CLOCK
DRIVER
XIN
VCC
OPTIONAL
OPTIONAL DRIVER
CLOCK
OUTPUT
XOUT
OSC CLOCK TO
BAUD GEN. LOGIC
GM16C550
are summed).
Bit 4: This bit is the Even Parity Select bit. When bit 3 is
a logic 1 and bit 4 is a logic 0, and odd number of logic
1s is transmitted or checked in the data word bits and
Parity bit. When bit 3is a logic 1 and it 4 is a logic 1, an
even number of logic 1s is transmitted or checked.
Bit 5: This bit is the Stick Parity bit. When bit3, 4 and 5
are logic 1 the Parity bit is transmitted and checked as a
logic 0. If bit 3 and 5 are 1 and bit 4 is a logic 0 then the
Parity bit is transmitted and checked as a logic 1. If bit
5 is a logic 0 Stick Parity is disabled.
Bit 6: This bit is the Break Control bit. It causes a break
condition to be transmitted to the received UART. When
it is set to logic 1, The serial output (SOUT) is forced to
the Spacing (logic 0) state. The break is disabled by
setting bit 6 to a logic 0. The Break Control bit acts only
on SOUT and has no effect on the transmitted logic.
Note : This feature enables the CPU to alert a terminal in
during the break. The Transmitter can be used as a
character timer to accurately establish the break duration.
a computer communications system.
If the following sequence is followed. no
erroneous or extraneous characters will be
transmitted because of the break.
1. Load on all Os, pad character, in response to THRE.
2. Set break after the next THRE
3. Wait for the transmitter to be idle. (TEMT = 1), and
clear break when normal transmission has to be tired.
During the bread, the Transmitter can be used as a
character timer to accurately establish the break duration.
Bit 7: This bit is the Divisor Latch Access Bit (DLAB).
It must be set high (logic) to access the Divisor Latches
of the Baud Generator during a Read or Write operation.
It must be set low (logic 0) to access the Receiver Buffer,
the Transmitter Holding Register, or the Interrupt Enable
Register.
VCC
XIN
C1
RP
CRYSTAL
R×2
XOUT
C2
OSC CLOCK TO
BAUD GEN. LOGIC
15
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