MC14052BDT データシートの表示（PDF） - ON Semiconductor
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MC14052BDT Datasheet PDF : 12 Pages
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MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally–controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
• Triple Diode Protection on Control Inputs
• Switch Function is Break Before Make
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
v • Analog Voltage Range (VDD – VEE) = 3.0 to 18 V
Note: VEE must be VSS
• Linearized Transfer Characteristics
• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053
• For 4PDT Switch, See MC14551B
• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed
CMOS Devices
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage (Referenced
– 0.5 to +18.0
V
to VEE, VSS ≥ VEE)
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5
V
(DC or Transient) (Referen–
ced to VSS for Control Inputs
and VEE for Switch I/O)
Iin
Input Current (DC or Transient)
± 10
mA
per Control Pin
ISW
Switch Through Current
PD
Power Dissipation,
per Package (Note 2.)
± 25
mA
500
mW
TA
Ambient Temperature Range
Tstg
Storage Temperature Range
TL
Lead Temperature
(8–Second Soldering)
– 55 to +125
°C
– 65 to +150
°C
260
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS, VEE or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC140XXBCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
140XXB
AWLYWW
1
TSSOP–16
DT SUFFIX
CASE 948F
16
14
0XXB
ALYW
1
SOEIAJ–16
F SUFFIX
CASE 966
16
MC140XXB
AWLYWW
1
XX
= Specific Device Code
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14051B/D
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