8212BM データシートの表示（PDF） - Nippon Precision Circuits

部品番号

コンポーネント説明

一致するリスト

8212BM

POCSAG Decoder For Multiframe Pagers

Nippon Precision Circuits  

PIN DESCRIPTION

SM8212B

Pin number

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Pin name

BS1

BS2

BS3

SIGNAL

XVSS

XT

XTN

VSS

CLKO

RSTN

AREA

SCK

SDO

SDI

ATTN

VDD

i/o

Description

o

RF control main output signal

o

RF DC-level adjustment signal

o

PLL setup signal

i

NRZ signal input pin

-

Crystal oscillator ground. Capacitor connected between XVSS and VDD

i

Oscillator input pin

o

Oscillator output pin

-

Ground

o

76.8 or 38.4 kHz clock output

i

Hardware clear (reset)

o

Sync code detection output (HIGH for minimum 1 sec. on detection)

i

CPU-to-decoder data transfer sync clock

o

Status and received data output to CPU

i

Data input from CPU (including ID data)

o

Interrupt detect signal output pin (Ready for data transmission when LOW)

-

Supply voltage

i = Input, o = Output

SM8212B Paging Receiver Block Diagram

RF

Waveform

Recovery

PLL Circuit

Supply Unit

D/D Converter

POCSAG

Decoder

SM8212

Alert

Melody

IC

SP

CPU Unit

ID

ROM

LCD Driver LCD

NIPPON PRECISION CIRCUITS-3

Share Link: