SG6860 データシートの表示（PDF） - Fairchild Semiconductor

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SG6860

Low-Cost, Green-Mode PWM Controller for Flyback Converters

Fairchild Semiconductor 

Functional Description

SG6860 integrates many useful designs into one

controller for low-power switch-mode power supplies.

The following descriptions highlight some of the

features of the SG6860 series.

Start-up Current

The start-up current is only 9µA, which allows a start-

up resistor with high resistance and low-wattage to

supply the start-up power for the controller. A 1.5MΩ,

0.25W, start-up resistor and a 10µF/25V VDD hold-up

capacitor are sufficient for an AC-to-DC power adapter

with a wide input range of 90VAC to 264VAC.

Operating Current

The operating current has been reduced to 3mA, which

results in higher efficiency and reduces the VDD hold-up

capacitance requirement.

Green-Mode Operation

The proprietary green-mode function provides off-time

modulation to linearly decrease the switching

frequency under light-load conditions. On-time is

limited to provide stronger protection against

brownouts and abnormal conditions. The feedback

current, which is sampled from the voltage feedback

loop, is taken as the reference. Once the feedback

current exceeds the threshold current, the switching

frequency starts to decrease. This green-mode

function dramatically reduces power consumption

under light-load and zero-load conditions. Power

supplies using the SG6860 can meet even strict

regulations regarding standby power consumption.

Oscillator Operation

A resistor connected from the RI pin to ground

generates a constant current source used to charge an

internal capacitor. The charge time determines the

internal clock speed and the switching frequency.

Increasing the resistance reduces the amplitude of the

input current and reduces the switching frequency. A

95kΩ resistor, RI, results in a 13µA constant current, II,

and a 70kHz switching frequency. The relationship

between RI and the switching frequency is:

fPWM

=

6650 (kHz)

RI (kΩ)

(1)

The range of the oscillation frequency is designed to

be within 50kHz ~ 100kHz.

Leading-Edge Blanking

Each time the power MOSFET is switched on, a turn-

on spike occurs at the sense-resistor. To avoid

premature termination of the switching pulse, a 300ns

leading-edge blanking time is built in. Conventional RC

filtering can therefore be omitted. During this blanking

period, the current-limit comparator is disabled and

cannot switch off the gate driver.

Constant Output Power Limit

When the SENSE voltage across the sense resistor,

RS, reaches the threshold voltage (~1.00V), the output

GATE drive is turned off after propagation delay, tPD.

This propagation delay introduces an additional current

proportional to tPD•VIN/Lp. The propagation delay is

nearly constant, regardless of the input line voltage VIN.

Higher input line voltages result in larger additional

currents. At high input line voltages, the output power

limit is higher than at low input line voltages.

To compensate for this output power limit variation

across a wide AC input range, the threshold voltage is

adjusted by adding a positive ramp. This ramp signal

rises from 0.70V to 1.00V, then flattens out at 1.00V. A

smaller threshold voltage forces the output GATE drive

to terminate earlier. This reduces the total PWM turn-

on time and makes the output power equal to that of

low line input. This proprietary internal compensation

ensures a constant output power limit for a wide AC

input voltage range (90VAC to 264VAC).

Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally

at 16.5V and 9.5V. During start-up, the hold-up

capacitor must be charged to 16.5V through the start-

up resistor to enable SG6860. The hold-up capacitor

continues to supply VDD until power can be delivered

from the auxiliary winding of the main transformer. VDD

must not drop below 9.5V during the start-up process.

This UVLO hysteresis window ensures that the hold-up

capacitor is adequate to supply VDD during start-up.

Gate Output

The SG6860 BiCMOS output stage is a fast totem pole

gate driver. Cross conduction has been avoided to

minimize heat dissipation, increase efficiency, and

enhance reliability. The output driver is clamped by an

internal 17V Zener diode to protect power MOSFET

transistors against undesired over-voltage gate signals.

Built-in Slope Compensation

The sensed voltage across the current sense resistor

is used for current mode control and pulse-by-pulse

current limiting. Built-in slope compensation improves

stability and prevents sub-harmonic oscillations due to

peak current mode control. The SG6860 has a

synchronized, positively-sloped ramp built-in at each

switching cycle. The slope of the ramp is:

0.36 × Duty

(2)

Duty(max .)

Noise Immunity

Noise from the current sense or the control signal can

cause significant pulse-width jitter, particularly in

continuous-conduction mode. While slope compensation

helps alleviate these problems, further precautions

should be taken. Good placement and layout practices

should be followed. Avoiding long PCB traces and

component leads, locating compensation and filter

components near the SG6860, and increasing power

MOS gate resistance improve performance.

© 2008 Fairchild Semiconductor Corporation

SG6860 • Rev. 1.0.0

8

www.fairchildsemi.com

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