SC92031 データシートの表示（PDF） - Silan Microelectronics

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SC92031

10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER

Silan Microelectronics 

SC92031

(Continued)

Bit R/W

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Symbol

TABT2

TABT1

TABT0

OWN3

OWN2

OWN1

OWN0

TABT bit of Descriptor2

TABT bit of Descriptor1

TABT bit of Descriptor0

OWN bit of Descriptor3

OWN bit of Descriptor2

OWN bit of Descriptor1

OWN bit of Descriptor0

Description

7 Tansmit Status Register (TX_STATUS0-3)(Offset 0020h-002Fh, R/W)

The read-only bits will be cleared by the chip when the Transmit Byte Count (bits 12-0) in the corresponding Tx

descriptor is written. It is not affected when software writes to these bits.

Bit R/W

Symbol

Description

31-

-

-

30

Reserved

29

R CRS

Carrier Sense Lost: This bit is set to 1 when the carrier is lost during

transmission of a packet.

28

R TABT

Transmit Abort: This bit is set to 1 if the transmission of a packet was

aborted.

Later Collision: This bit is set to 1 if the chip encountered an later

27

R Later Collision

collision during the transmission of a packet.

26

-

-

Reserved

Collision Count: Indicates the number of collisions encountered during

25-22 R Collision Counter

the transmission of a packet.

Early Tx Threshold: Specifies the threshold level in the Tx FIFO to

21-

Early

R/W

16

Threshold

begin the transmission. When the byte count of the data in the Tx FIFO

Tx

reaches this level, (or the FIFO contains at least one complete packet)

the chip will transmit this packet. These fields count from 000001 to

111111 in unit of 32 bytes.

15

R TOK

Transmit Success: This bit is set to 1 if the transmission of a packet

was successed.

14

R TUN

Tx FIFO Underrun: Set to 1 if the Tx FIFO was exhausted during the

transmission of a packet.

OWN: The chip sets this bit to 1 when the Tx DMA operation of this

13 R/W OWN

descriptor was completed. The driver must set this bit to 0 when the

Transmit Byte Count (bits 0-12) is written. The default value is 1.

12-0 R/W SIZE

Descriptor Size: The total size in bytes of the data in this descriptor.

8 Tansmit Start Address of Descriptor Register (TX_ADDR0-3)(Offset 0030h-003Fh, R/W)

Bit R/W

Symbol

Description

31-0 R/W TSAD

Transmit Start Address of Descriptor

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

Http: www.silan.com.cn

REV:1.0 2004.08.03

Page 11 of 38

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