SC1406A データシートの表示（PDF） - Semtech Corporation
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SC1406A Datasheet PDF : 17 Pages
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PORTABLE PENTIUM® II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
In DSPS hysteretic controller configuration
(Cont’d)
The comparator reference voltage positioning is such
that an increasing current sense voltage, VCS, i,e, an
elevating load current, causes the reference voltage to
decrease, and as a consequence, the core output volt-
age also droops. At no load current, there is no droop
while a maximum load, the droop is likewise maxi-
mum.
In order for the core voltage to be positioned around
the nominal VDAC voltage symmetrically and not just
one way downward from the nominal value, a DSPS
offset voltage, VDSPSOFFS, can be introduced. The off-
set voltage moves the comparator reference voltage
upward at no load. At optimal offsetting, the reference
voltage is above the nominal level for load currents
less than half of the maximum load, and below the
nominal value for currents higher than that. The maxi-
mum amount of core voltage positioning can be deter-
mined from the constrain which says the output volt-
age at no load condition must still remain below the
upper threshold of the core voltage regulation window,
and at maximum load, it must be above the lower
threshold.
The offset voltage can be generated across a resistor,
ROH, which is also used to create the hysteresis volt-
age by forcing a unipolar DSPS offsetting current
through it. The offsetting current is conveniently pro-
vided by a high value resistor, ROFFSET, connected from
the comparator CMP pin to the ground.
V DSPSOFFS
=
R OH
•
IDSPS
=
R
OH •
VCS + VCORE
R OH +R OFFSET
≈ RR •V VCS << VCORE ,VCORE = VDAC ,ROH <<ROFFSET
OH
OFFSET
DAC
In DSPS hysterestic controller configuration, the com-
parator thresholds can be calculated from the DAC
voltage, VDAC, the DSPS offsetting voltage, VDSPSOFFS,
the DSPS voltage VDSPS, and the bipolar hysteresis
voltage, VHYST by summing them at the comparator in-
puts at the appropriate load current levels:
Core Voltage Offsetting
In order for the core voltage to be positioned around
the nominal VDAC voltage symmetrically and not just
always one direction downward, a core offset voltage,
VOFFS can be introduced. The offset voltage moves the
comparator reference voltage upwards. Using optimal
offsetting, the core comparator reference voltage will
be above the VID programmed nominal DAC voltage
for load currents less than half of the maximum load,
and below that for higher current. The maximum
amount of the core voltage positioning can be deter-
mined from the constraint that the output voltage regu-
lation window, and at maximum load, it has to be
above the lower threshold.
The positioning offset voltage can be generated
across the same resistor, ROH also used to create the
hysteresis voltage, by forcing a unipolar offsetting cur-
rent through it. The offsetting current is conveniently
provided by a high value resistor, ROFFS connected
from the comparator CMP pin to the ground.
Current Limit Comparator
The current limit comparator monitors the core con-
verter output current and turns the high side switch off
when the current exceeds the upper current limit
threshold, VHCL and re-enable only if the load current
drops below the lower current limit threshold, VLCL.
The current is sensed by monitoring the voltage drop
across the current sense resistor, RCS, connected in
series with the core converter main inductor (the same
resistor used for DSPS input signal generation). The
thresholds have the following relationships:
VHCL
= 3 • R CLOH
R CLSET
•V REF
VLCL
= 2 • R CLOH
R CLSET
•V REF
VHYSCL
= R CLOH
R CLSET
•V REF
Vcore := Vdac • (Roffset + Roh ) • Rcore − Rcs • Icore • Roffset • (Rcore + Rdac )
Rcore • Roffset − Rdac • Roh
∆Vcore
:=
2
•
Vhys
•
Rcore • (Roffset + Roh)
Rcore • Roffset − Rdac • Roh
•
Re
sr
+
Re sr
Rcore • (Roffset + Roh )
Rcore • Roffset − Rdac • Roh
© 2000 SEMTECH CORP.
Pentium is a registered trademark of Intel Corporation
10
652 MITCHELL ROAD NEWBURY PARK CA 91320
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