SAA7199B データシートの表示（PDF） - Philips Electronics
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SAA7199B Datasheet PDF : 40 Pages
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Philips Semiconductors
Digital Video Encoder (DENC)
GENLOCK-capable
Product specification
SAA7199B
Timing (see Fig.3)
The reference to generate internal clocks from LLC in
GENLOCK operation with SAA7197 is CREF
CREF = L----L-2---C--- .
In this event input CLKSEL is HIGH and the SRC-bit = 1.
In non-GENLOCK operation the signal from CLKIN is used
and LDV is clock reference (input CLKSEL = 0;
SCR-bit = CPR-bit = 0).
Pins LLC and CLKIN are tied together when no switching
between LLC and CLKIN is applied. In Fig.3 it is assumed
that LLC and CLKIN are double the pixel clock frequency
of CREF and LDV respectively.
CREF must be at the same frequency (or constant HIGH
or LOW) when LLC is at pixel clock frequency. CPR-bit = 1
if CLKIN is at pixel clock frequency.
The buffered CLKO signal is always delayed. LLC or
CLKIN signals are in accordance with CLKSEL.
Mapping
The method of mapping external control signals on to the
internal bus is simple. The MPU-bus contains the signals
as shown in Table 4 (names in chip-internal
nomenclature).
Bit allocation
The Bit Allocation Map (BAM) shows the individual control
signals, used to control the different operational modes of
the circuit. The I2C-bus is normally used for control.
The SAA7199B also has an MPU-bus interface for direct
microcontroller connection. The BAM shown in Table 6
resembles the I2C-bus type but can be also used for the
parallel bus; the control registers are indexed from
00H to 0FH. Auto-incrementation is applied.
Digital-to-analog converters
The converters use a combination of resistor chains with
low-impedance output buffers. The bottom output voltage
is 200 mV to reduce integral non-linearity errors.
The analog signal, without load on output pin, is between
0.2 and 2.2 V. Figure 16 shows the application for
1.23 V/75 Ω outputs, using the serial 25 + 22 Ω resistors.
Each digital-to-analog converter has its own supply pin for
the purpose of decoupling. VDDA4 is the supply voltage for
the resistor chains of the three DACs. The accuracy of this
supply voltage directly influences the output amplitudes.
The current CUR into pin 71 is 0.3 mA (VDDA4 = 5 V;
R64-71 = 20 kΩ); a larger current improves the bandwidth
but increases the integral non-linearity.
Table 1 Pixel relationships
ACTIVE PIXELS
PER LINE
640 (square)
720
768
720
FIELD RATE
(Hz)
60
60
50
50
MULTIPLES OF LINE
FREQUENCY
780
858
944
864
PIXCLK OUTPUT SIGNAL
(MHz)
12.27
13.5
14.75
13.5
CRYSTAL
(MHz)
26.8
24.576
26.8
24.576
Table 2 Access to the control interface
SYMBOL
SDA
SCL
A1, A0
R/W
CS
GPSW
RESET
DESCRIPTION
I2C-bus serial data line (bidirectional)
I2C-bus clock line
MPU-bus address inputs
read/write control input
chip select input; I2C-bus disabled when LOW
general purpose switch output (bit of control register)
reset input signal; active-LOW
1996 Sep 27
9
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