SAA7188A データシートの表示（PDF） - Philips Electronics
部品番号
コンポーネント説明
一致するリスト
SAA7188A Datasheet PDF : 36 Pages
| |||
Philips Semiconductors
Digital Video Encoder (DENC2-M)
Preliminary specification
SAA7188A
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the IC can
output:
• A Vertical Sync signal (VS) with 3 or 2.5 lines duration,
or
• An ODD/EVEN signal which is LOW in odd fields, or
• A field sequence signal (FSEQ) which is HIGH in the first
of 4 respectively 8 fields.
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up e.g. a
composite blanking signal.
The phase of the pulses output on RCV1 or RCV2 are
referenced to the VP port, polarity of both signals is
selectable.
The DENC2-M is always the timing master for the source
at the MP input. The IC provides two signals for
synchronizing this source:
On the RCM1 port the same signals as on RCV1 (as
output) are available; on RCM2 the IC provides a
horizontal pulse with programmable start and stop
phase.
The length of a field also start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.
Control interface
DENC2-M contains two control interfaces: an I2C-bus
slave transceiver and 8-bit parallel microprocessor
interface. The interfaces cannot be used simultaneously.
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 100 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
Two I2C-bus slave addresses can be selected
(pin SEL_MPU must be LOW):
88H: LOW at pin 61
8CH: HIGH at pin 61.
The parallel interface is defined by:
D7 to D0 data bus
CS active-LOW chip select signal
RW read/not write signal, LOW for a write cycle
DTACK 680XX style data acknowledge (handshake),
active-LOW
A0 register select, LOW selects address, HIGH selects
data.
The parallel interface uses two registers, one
auto-incremental containing the current address of a
control register (equals subaddress with I2C-bus control),
one containing actual data. The currently addressed
register is mapped to the corresponding control register.
The status byte can be read optionally via a read access
to the address register, no other read access is provided.
Input levels and formats
DENC2-M expects digital YUV data with levels (digital
codes) in accordance with CCIR 601.
Deviating amplitudes of the colour difference signals can
be compensated by independent gain control setting,
while gain for luminance is set to predefined values,
distinguishable for 7.5 IRE set-up or without set-up.
The MPEG port accepts only 8-bit multiplexed CCIR 656
compatible data.
If the I2C-bus interface is used, the VP port can handle
both formats, 8-bit multiplexed Cb-Y-Cr data on the
VP lines, or the 16-bit DTV2 format with the Y signal on the
VP lines and the UV signal on the DP port.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
1996 Jul 08
9
Share Link: 