SAA7184 データシートの表示（PDF） - Philips Electronics
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SAA7184 Datasheet PDF : 36 Pages
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Philips Semiconductors
Digital Video Encoders (DENC2-M6)
Preliminary specification
SAA7184; SAA7185B
The luminance gain and offset are modified (offset being
programmable within a certain range to enable different
black level set-ups). After the signals have been inserted,
a fixed synchronization level in accordance with standard
composite synchronization schemes and blanking level,
(also programmable in a certain range to allow for
manipulations with Macrovision anti-tapping) additional
insertion of AGC super white pulses (programmable in
height) is supported.
In order to enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, thereby providing luminance in a 10-bit resolution.
This filter is also used to define smoothed transients for
synchronization pulses and blanking period. The transfer
characteristics of the luminance interpolation filter are
illustrated in Figs 5 and 6.
The chrominance gain is modified (programmable
separately for U and V), a standard dependent burst is
inserted before baseband colour signals are interpolated
from a 6.75 MHz data rate to a 27 MHz data rate. One of
the interpolation stages can be bypassed, thereby
providing a higher colour bandwidth, which can be used for
the Y/C output. The transfer characteristics of the
chrominance interpolation filter are illustrated in
Figs 3 and 4.
The amplitude of the inserted burst is programmable within
a certain range, suitable for standard signals and for
special effects. Colour in a 10-bit resolution is provided on
the subcarrier after the succeeding quadrature modulator.
The numeric ratio between Y and C outputs is in
accordance with set standards.
CLOSED CAPTION ENCODER
Using the closed caption encoder circuit, data in
accordance with the specification of closed caption or
extended data service, delivered by the control interface,
can be encoded (line 21). Two dedicated pairs of bytes
(two bytes per field) are possible, each pair preceded by
run-in clocks and framing code.
The actual line number where data is to be encoded, can
be modified within a certain range.
The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
It is also possible to encode closed caption data for 50 Hz
field frequencies at 32 times horizontal line frequency.
Output interface
In the output interface, encoded Y and C signals are
converted from digital to analog in a 10-bit resolution and
then combined into a 10-bit CVBS signal. Also, in front of
the summation point, the luminance signal can be fed
through a further filter stage (optional), thereby
suppressing components in the subcarrier frequency
range. Thus, a type of cross colour reduction is provided,
which is useful in a standard TV set with CVBS input.
The slopes of the synchronization pulses are not affected
with any active cross colour reduction.
Three different filter characteristics or bypass are
available, see Fig.5.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitudes at the input
of the DAC for CVBS is reduced by 15⁄16 with respect to Y
and C DACs to make maximum use of conversion ranges.
Outputs of all DACs can be set together, via software
control, to minimum output voltage for either purpose.
Synchronization
The synchronization of the DENC2 is able to operate in
two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour, related to the video signal on VP
(and DP, if used), can be influenced by programming the
polarity and on-chip delay of RCV1. The active slope of
RCV1 defines the vertical phase and, as an option, the
odd/even and colour frame phase to be initialized. It can
also be used to set the horizontal phase.
If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be applied at pin RCV2. Timing
and trigger behaviour can also be influenced for RCV2.
If there are missing pulses at RCV1 and/or RCV2, the time
base of the DENC2-M6 will become free-running, thus an
arbitrary number of synchronization slopes may miss, but
no additional pulses must occur (such as with wrong
phase).
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
1996 Jul 03
8
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