SAA7134 データシートの表示（PDF） - Philips Electronics
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SAA7134 Datasheet PDF : 52 Pages
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Philips Semiconductors
PCI audio and video broadcast decoder
Product specification
SAA7134HL
6.2 Pins grouped by function
Table 2 Power supply pins
SYMBOL
VSSA
VDDA
VSSD
VDDD
PIN
TYPE
97, 108, 113 AG
and 119
95, 110 AS
and 115
20, 39, 55, VG
64, 74, 93
and 128
1, 19, 38, 54, VS
65, 73
and 92
DESCRIPTION
analog ground for integrated analog signal processing
analog supply voltage for integrated analog signal processing
digital ground for digital circuit, core and I/Os
digital supply voltage for digital circuit, core and I/Os
Table 3 PCI interface pins; note 1
SYMBOL
PCI_CLK
PCI_RST#
AD[31] to
AD[00]
C/BE[3]# to
C/BE[0]#
PAR
FRAME#
TRDY#
IRDY#
STOP#
IDSEL
DEVSEL#
REQ#
GNT#
PIN
TYPE
DESCRIPTION
40
PI
PCI clock input: reference for all bus transactions, up to 33.33 MHz
127
PI
PCI reset input: will 3-state all PCI pins (active LOW)
4 to 11,
14 to 18,
21 to 23,
34 to 37,
41 to 44 and
46 to 53
PIO and
T/S
multiplexed address and data input or output: bi-directional, 3-state
12, 24, 33 PIO and command code input or output: indicates type of requested transaction and
and 45 T/S
byte enable, for byte aligned transactions (active LOW)
32
PIO and parity input or output: driven by the data source, even parity over all pins AD
T/S
and C/BE#
25
PIO and frame input or output: driven by the current bus master (owner), to indicate
S/T/S the beginning and duration of a bus transaction (active LOW)
27
PIO and target ready input or output: driven by the addressed target, to indicate
S/T/S readiness for requested transaction (active LOW)
26
PIO and initiator ready input or output: driven by the initiator, to indicate readiness to
S/T/S continue transaction (active LOW)
29
PIO and stop input or output: target is requesting the master to stop the current
S/T/S transaction (active LOW)
13
PI
initialization device select input: this input is used to select the SAA7134HL
during configuration read and write transactions
28
PIO and device select input or output: driven by the target device, to acknowledge
S/T/S address decoding (active LOW)
3
PO
PCI request output: the SAA7134HL requests master access to PCI-bus
(active LOW)
2
PI
PCI grant input: the SAA7134HL is granted to master access PCI-bus
(active LOW)
2002 Dec 17
10
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