CY7C025AV-20AI データシートの表示（PDF） - Cypress Semiconductor

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CY7C025AV-20AI

3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

Cypress Semiconductor 

PRELIMINARY

Switching Waveforms (continued)

Interrupt Timing Diagrams

Left Side Sets INTR :

ADDRESSL

CE L

tWC

WRITE 1FFF (OR 1/3FFF)

tHA[43]

R/W L

INT R

Right Side Clears INTR:

ADDRESSR

CER

R/WR

OE R

INTR

Right Side Sets INTL:

ADDRESSR

CE R

tINS [44]

tINR [44]

tWC

WRITE 1FFE (OR 1/3FFE)

tHA[43]

R/W R

INT L

Left Side Clears INT L:

ADDRESSR

tINS[44]

CE L

R/W L

tINR[44]

OE L

INT L

Notes:

43. tHA depends on which enable pin (CEL or R/WL) is deasserted first.

44. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.

14

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

tRC

READ 7FFF

(OR 1/3FFF)

tRC

READ 7FFE

OR 1/3FFE)

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