HIP4080 データシートの表示（PDF） - Intersil
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HIP4080 Datasheet PDF : 21 Pages
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HIP4080
Switching Specifications
VDD
CL =
= VCC =
1000pF,
aVnAdHBTA==V2B5HoBC=, U1n2lVe,sVsSOSth=eVrwAiLsSe
= VBLS =
Specified
VAHS = VBHS
(Continued)
=
0V,
RHDEL
=
RLDEL
=
10K,
TJ = 25oC
TTJO=1-2450ooCC
PARAMETERS
SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW
- 45 75 - 95 ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH
- 55 85 - 105 ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
TDLPLH
- 35 70 - 90 ns
Refresh Pulse Width (ALO and BLO)
Disable to Upper Enable (DIS - AHO and BHO)
HEN-AHO, BHO Turn-off, Propagation Delay
HEN-AHO, BHO Turn-on, Propagation Delay
TREF-PW
160 260 380 140 420 ns
TUEN
- 335 500 - 550 ns
THEN-PHL RHDEL = RLDEL = 10K -
35 70
-
90
ns
THEN-PLH RHDEL = RLDEL = 10K -
60 90
- 110 ns
IN+ > IN-
X
1
0
1
0
INPUT
HEN
X
1
1
0
0
TRUTH TABLE
DIS
ALO
1
0
0
0
0
1
0
0
0
1
OUTPUT
AHO
BLO
0
0
1
1
0
0
0
1
0
0
BHO
0
0
1
0
0
Pin Descriptions
PIN
NUMBER
1
2
3
4
5
6
7
8
SYMBOL
DESCRIPTION
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
HEN
DIS
VSS
OUT
High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers
(Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can
be driven by signal levels of 0V to 15V (no greater than VDD).
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than VDD).
Chip negative supply, generally will be ground.
OUTput of the input control comparator. This output can be used for feedback and hysteresis.
IN+
Non-inverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs
and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO
and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level
will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg
is controlled by HDEL and LDEL (Pins 8 and 9).
IN-
Inverting input of control comparator. See IN+ (Pin 6) description.
HDEL
High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
6
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